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Searched refs:AMDGPUInstrInfo (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.cpp31 void AMDGPUInstrInfo::anchor() {} in anchor()
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &ST) in AMDGPUInstrInfo() function in AMDGPUInstrInfo
36 bool AMDGPUInstrInfo::enableClusterLoads() const { in enableClusterLoads()
50 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, in shouldScheduleLoadsNear()
62 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { in getMaskedMIMGOp()
107 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const { in pseudoToMCOpcode()
DAMDGPUInstrInfo.h38 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
45 explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
DAMDGPUSubtarget.h119 const AMDGPUInstrInfo *getInstrInfo() const override;
432 inline const AMDGPUInstrInfo *AMDGPUSubtarget::getInstrInfo() const { in getInstrInfo()
DAMDGPU.td341 def AMDGPUInstrInfo : InstrInfo {
354 let InstructionSet = AMDGPUInstrInfo;
400 include "AMDGPUInstrInfo.td"
DCMakeLists.txt48 AMDGPUInstrInfo.cpp
DR600InstrInfo.h29 class R600InstrInfo final : public AMDGPUInstrInfo {
DAMDGPUInstrInfo.td1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
DSIInstrInfo.h25 class SIInstrInfo final : public AMDGPUInstrInfo {
DR600InstrInfo.cpp32 : AMDGPUInstrInfo(ST), RI(), ST(ST) {} in R600InstrInfo()
905 return AMDGPUInstrInfo::isPredicable(MI); in isPredicable()
DSIInstrInfo.cpp32 : AMDGPUInstrInfo(ST), RI(), ST(ST) {} in SIInstrInfo()
854 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI); in expandPostRAPseudo()
DSIInstrInfo.td87 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.cpp29 AMDGPUInstrInfo::AMDGPUInstrInfo(const GCNSubtarget &ST) { } in AMDGPUInstrInfo() function in AMDGPUInstrInfo
33 bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) { in isUniformMMO()
DAMDGPUInstrInfo.h30 class AMDGPUInstrInfo {
32 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
DR600.td38 include "AMDGPUInstrInfo.td"
DAMDGPUInstructionSelector.h33 class AMDGPUInstrInfo; variable
DCMakeLists.txt44 AMDGPUInstrInfo.cpp
DAMDGPU.td558 def AMDGPUInstrInfo : InstrInfo {
616 let InstructionSet = AMDGPUInstrInfo;
729 include "AMDGPUInstrInfo.td"
DAMDGPUInstrInfo.td1 //===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
DAMDGPURegisterBankInfo.cpp189 return AMDGPUInstrInfo::isUniformMMO(MMO); in isInstrUniform()
DSIInstrInfo.td26 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
DSIISelLowering.cpp1145 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand()); in isMemOpUniform()