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Searched refs:APLL_HZ (Results 1 – 18 of 18) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
99 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; in rkclk_init()
100 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); in rkclk_init()
102 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()
103 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()
Dclk_rk322x.c38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
100 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; in rkclk_init()
101 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); in rkclk_init()
103 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()
104 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()
Dclk_rk3128.c35 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
161 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; in rkclk_init()
162 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); in rkclk_init()
164 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; in rkclk_init()
165 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); in rkclk_init()
Dclk_rk3328.c315 clk_core_div = APLL_HZ / CLK_CORE_HZ - 1; in rk3328_configure_cpu()
316 aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1; in rk3328_configure_cpu()
317 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1; in rk3328_configure_cpu()
Dclk_rk3188.c187 case APLL_HZ: in rkclk_configure_cpu()
567 rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj); in rk3188_clk_probe()
Dclk_rk3308.c985 priv->cru, APLL) != APLL_HZ) { in rk3308_clk_init()
986 ret = rk3308_armclk_set_clk(priv, APLL_HZ); in rk3308_clk_init()
Dclk_px30.c1414 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) in px30_clk_probe()
1415 px30_armclk_set_clk(priv, APLL_HZ); in px30_clk_probe()
Dclk_rv1108.c40 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
Dclk_rk3288.c140 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3328.h50 #define APLL_HZ (600 * MHz) macro
Dcru_rk3188.h10 #define APLL_HZ (1608 * 1000000) macro
Dcru_rk3036.h12 #define APLL_HZ (600 * 1000000) macro
Dcru_rk322x.h13 #define APLL_HZ (600 * MHz) macro
Dcru_rk3128.h14 #define APLL_HZ (600 * MHz) macro
Dcru_rk3288.h13 #define APLL_HZ (1800 * 1000000) macro
Dcru_rv1108.h13 #define APLL_HZ (600 * 1000000) macro
Dcru_px30.h14 #define APLL_HZ (600 * MHz) macro
/external/u-boot/arch/arm/include/asm/arch-rk3308/
Dcru_rk3308.h13 #define APLL_HZ (816 * MHz) macro