1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd. 4 */ 5 #ifndef _ASM_ARCH_CRU_RK3308_H 6 #define _ASM_ARCH_CRU_RK3308_H 7 8 #include <common.h> 9 10 #define MHz 1000000 11 #define OSC_HZ (24 * MHz) 12 13 #define APLL_HZ (816 * MHz) 14 15 #define CORE_ACLK_HZ 408000000 16 #define CORE_DBG_HZ 204000000 17 18 #define BUS_ACLK_HZ 200000000 19 #define BUS_HCLK_HZ 100000000 20 #define BUS_PCLK_HZ 100000000 21 22 #define PERI_ACLK_HZ 200000000 23 #define PERI_HCLK_HZ 100000000 24 #define PERI_PCLK_HZ 100000000 25 26 #define AUDIO_HCLK_HZ 100000000 27 #define AUDIO_PCLK_HZ 100000000 28 29 #define RK3308_PLL_CON(x) ((x) * 0x4) 30 #define RK3308_MODE_CON 0xa0 31 32 /* RK3308 pll id */ 33 enum rk3308_pll_id { 34 APLL, 35 DPLL, 36 VPLL0, 37 VPLL1, 38 PLL_COUNT, 39 }; 40 41 struct rk3308_clk_info { 42 unsigned long id; 43 char *name; 44 }; 45 46 /* Private data for the clock driver - used by rockchip_get_cru() */ 47 struct rk3308_clk_priv { 48 struct rk3308_cru *cru; 49 ulong armclk_hz; 50 ulong dpll_hz; 51 ulong vpll0_hz; 52 ulong vpll1_hz; 53 }; 54 55 struct rk3308_cru { 56 struct rk3308_pll { 57 unsigned int con0; 58 unsigned int con1; 59 unsigned int con2; 60 unsigned int con3; 61 unsigned int con4; 62 unsigned int reserved0[3]; 63 } pll[4]; 64 unsigned int reserved1[8]; 65 unsigned int mode; 66 unsigned int misc; 67 unsigned int reserved2[2]; 68 unsigned int glb_cnt_th; 69 unsigned int glb_rst_st; 70 unsigned int glb_srst_fst; 71 unsigned int glb_srst_snd; 72 unsigned int glb_rst_con; 73 unsigned int pll_lock; 74 unsigned int reserved3[6]; 75 unsigned int hwffc_con0; 76 unsigned int reserved4; 77 unsigned int hwffc_th; 78 unsigned int hwffc_intst; 79 unsigned int apll_con0_s; 80 unsigned int apll_con1_s; 81 unsigned int clksel_con0_s; 82 unsigned int reserved5; 83 unsigned int clksel_con[74]; 84 unsigned int reserved6[54]; 85 unsigned int clkgate_con[15]; 86 unsigned int reserved7[(0x380 - 0x338) / 4 - 1]; 87 unsigned int ssgtbl[32]; 88 unsigned int softrst_con[10]; 89 unsigned int reserved8[(0x480 - 0x424) / 4 - 1]; 90 unsigned int sdmmc_con[2]; 91 unsigned int sdio_con[2]; 92 unsigned int emmc_con[2]; 93 }; 94 95 enum { 96 /* PLLCON0*/ 97 PLL_BP_SHIFT = 15, 98 PLL_POSTDIV1_SHIFT = 12, 99 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 100 PLL_FBDIV_SHIFT = 0, 101 PLL_FBDIV_MASK = 0xfff, 102 103 /* PLLCON1 */ 104 PLL_PDSEL_SHIFT = 15, 105 PLL_PD1_SHIFT = 14, 106 PLL_PD_SHIFT = 13, 107 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 108 PLL_DSMPD_SHIFT = 12, 109 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 110 PLL_LOCK_STATUS_SHIFT = 10, 111 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 112 PLL_POSTDIV2_SHIFT = 6, 113 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 114 PLL_REFDIV_SHIFT = 0, 115 PLL_REFDIV_MASK = 0x3f, 116 117 /* PLLCON2 */ 118 PLL_FOUT4PHASEPD_SHIFT = 27, 119 PLL_FOUTVCOPD_SHIFT = 26, 120 PLL_FOUTPOSTDIVPD_SHIFT = 25, 121 PLL_DACPD_SHIFT = 24, 122 PLL_FRAC_DIV = 0xffffff, 123 124 /* CRU_MODE */ 125 PLLMUX_FROM_XIN24M = 0, 126 PLLMUX_FROM_PLL, 127 PLLMUX_FROM_RTC32K, 128 USBPHY480M_MODE_SHIFT = 8, 129 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT, 130 VPLL1_MODE_SHIFT = 6, 131 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT, 132 VPLL0_MODE_SHIFT = 4, 133 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT, 134 DPLL_MODE_SHIFT = 2, 135 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, 136 APLL_MODE_SHIFT = 0, 137 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, 138 139 /* CRU_CLK_SEL0_CON */ 140 CORE_ACLK_DIV_SHIFT = 12, 141 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT, 142 CORE_DBG_DIV_SHIFT = 8, 143 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT, 144 CORE_CLK_PLL_SEL_SHIFT = 6, 145 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT, 146 CORE_CLK_PLL_SEL_APLL = 0, 147 CORE_CLK_PLL_SEL_VPLL0, 148 CORE_CLK_PLL_SEL_VPLL1, 149 CORE_DIV_CON_SHIFT = 0, 150 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 151 152 /* CRU_CLK_SEL5_CON */ 153 BUS_PLL_SEL_SHIFT = 6, 154 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT, 155 BUS_PLL_SEL_DPLL = 0, 156 BUS_PLL_SEL_VPLL0, 157 BUS_PLL_SEL_VPLL1, 158 BUS_ACLK_DIV_SHIFT = 0, 159 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 160 161 /* CRU_CLK_SEL6_CON */ 162 BUS_PCLK_DIV_SHIFT = 8, 163 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT, 164 BUS_HCLK_DIV_SHIFT = 0, 165 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT, 166 167 /* CRU_CLK_SEL7_CON */ 168 CRYPTO_APK_SEL_SHIFT = 14, 169 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT, 170 CRYPTO_PLL_SEL_DPLL = 0, 171 CRYPTO_PLL_SEL_VPLL0, 172 CRYPTO_PLL_SEL_VPLL1 = 0, 173 CRYPTO_APK_DIV_SHIFT = 8, 174 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 175 CRYPTO_PLL_SEL_SHIFT = 6, 176 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT, 177 CRYPTO_DIV_SHIFT = 0, 178 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 179 180 /* CRU_CLK_SEL8_CON */ 181 DCLK_VOP_SEL_SHIFT = 14, 182 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 183 DCLK_VOP_SEL_DIVOUT = 0, 184 DCLK_VOP_SEL_FRACOUT, 185 DCLK_VOP_SEL_24M, 186 DCLK_VOP_PLL_SEL_SHIFT = 10, 187 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT, 188 DCLK_VOP_PLL_SEL_DPLL = 0, 189 DCLK_VOP_PLL_SEL_VPLL0, 190 DCLK_VOP_PLL_SEL_VPLL1, 191 DCLK_VOP_DIV_SHIFT = 0, 192 DCLK_VOP_DIV_MASK = 0xff, 193 194 /* CRU_CLK_SEL25_CON */ 195 /* CRU_CLK_SEL26_CON */ 196 /* CRU_CLK_SEL27_CON */ 197 /* CRU_CLK_SEL28_CON */ 198 CLK_I2C_PLL_SEL_SHIFT = 14, 199 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT, 200 CLK_I2C_PLL_SEL_DPLL = 0, 201 CLK_I2C_PLL_SEL_VPLL0, 202 CLK_I2C_PLL_SEL_24M, 203 CLK_I2C_DIV_CON_SHIFT = 0, 204 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT, 205 206 /* CRU_CLK_SEL29_CON */ 207 CLK_PWM_PLL_SEL_SHIFT = 14, 208 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT, 209 CLK_PWM_PLL_SEL_DPLL = 0, 210 CLK_PWM_PLL_SEL_VPLL0, 211 CLK_PWM_PLL_SEL_24M, 212 CLK_PWM_DIV_CON_SHIFT = 0, 213 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 214 215 /* CRU_CLK_SEL30_CON */ 216 /* CRU_CLK_SEL31_CON */ 217 /* CRU_CLK_SEL32_CON */ 218 CLK_SPI_PLL_SEL_SHIFT = 14, 219 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT, 220 CLK_SPI_PLL_SEL_DPLL = 0, 221 CLK_SPI_PLL_SEL_VPLL0, 222 CLK_SPI_PLL_SEL_24M, 223 CLK_SPI_DIV_CON_SHIFT = 0, 224 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 225 226 /* CRU_CLK_SEL34_CON */ 227 CLK_SARADC_DIV_CON_SHIFT = 0, 228 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT, 229 230 /* CRU_CLK_SEL36_CON */ 231 PERI_PLL_SEL_SHIFT = 6, 232 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT, 233 PERI_PLL_DPLL = 0, 234 PERI_PLL_VPLL0, 235 PERI_PLL_VPLL1, 236 PERI_ACLK_DIV_SHIFT = 0, 237 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 238 239 /* CRU_CLK_SEL37_CON */ 240 PERI_PCLK_DIV_SHIFT = 8, 241 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT, 242 PERI_HCLK_DIV_SHIFT = 0, 243 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT, 244 245 /* CRU_CLKSEL41_CON */ 246 EMMC_CLK_SEL_SHIFT = 15, 247 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 248 EMMC_CLK_SEL_EMMC = 0, 249 EMMC_CLK_SEL_EMMC_DIV50, 250 EMMC_PLL_SHIFT = 8, 251 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT, 252 EMMC_SEL_DPLL = 0, 253 EMMC_SEL_VPLL0, 254 EMMC_SEL_VPLL1, 255 EMMC_SEL_24M, 256 EMMC_DIV_SHIFT = 0, 257 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 258 259 /* CRU_CLKSEL43_CON */ 260 MAC_CLK_SPEED_SEL_SHIFT = 15, 261 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT, 262 MAC_CLK_SPEED_SEL_10M = 0, 263 MAC_CLK_SPEED_SEL_100M, 264 MAC_CLK_SOURCE_SEL_SHIFT = 14, 265 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT, 266 MAC_CLK_SOURCE_SEL_INTERNAL = 0, 267 MAC_CLK_SOURCE_SEL_EXTERNAL, 268 MAC_PLL_SHIFT = 6, 269 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT, 270 MAC_SEL_DPLL = 0, 271 MAC_SEL_VPLL0, 272 MAC_SEL_VPLL1, 273 MAC_DIV_SHIFT = 0, 274 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT, 275 276 /* CRU_CLK_SEL45_CON */ 277 AUDIO_PCLK_DIV_SHIFT = 8, 278 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT, 279 AUDIO_PLL_SEL_SHIFT = 6, 280 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT, 281 AUDIO_PLL_VPLL0 = 0, 282 AUDIO_PLL_VPLL1, 283 AUDIO_PLL_24M, 284 AUDIO_HCLK_DIV_SHIFT = 0, 285 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT, 286 }; 287 288 check_member(rk3308_cru, emmc_con[1], 0x494); 289 290 #endif 291