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Searched refs:CLK2MHZ (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/arch/arm/mach-rmobile/
Dtimer.c17 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
41 timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); in get_time_us()
42 do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); in get_time_us()
66 wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); in __udelay()
/external/u-boot/board/renesas/eagle/
Deagle.c37 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
49 stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; in s_init()
/external/u-boot/board/renesas/stout/
Dstout.c36 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
49 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init()
/external/u-boot/board/renesas/gose/
Dgose.c30 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
42 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; in s_init()
/external/u-boot/board/renesas/porter/
Dporter.c32 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
44 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; in s_init()
/external/u-boot/board/renesas/koelsch/
Dkoelsch.c32 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
44 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; in s_init()
/external/u-boot/board/renesas/lager/
Dlager.c34 #define CLK2MHZ(clk) (clk / 1000 / 1000) macro
47 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init()