1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout.c
4 * This file is Stout board support.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
9 */
10
11 #include <common.h>
12 #include <env.h>
13 #include <malloc.h>
14 #include <netdev.h>
15 #include <dm.h>
16 #include <dm/platform_data/serial_sh.h>
17 #include <env_internal.h>
18 #include <asm/processor.h>
19 #include <asm/mach-types.h>
20 #include <asm/io.h>
21 #include <linux/errno.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/gpio.h>
24 #include <asm/arch/rmobile.h>
25 #include <asm/arch/rcar-mstp.h>
26 #include <asm/arch/mmc.h>
27 #include <asm/arch/sh_sdhi.h>
28 #include <miiphy.h>
29 #include <i2c.h>
30 #include <mmc.h>
31 #include "qos.h"
32 #include "cpld.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)37 void s_init(void)
38 {
39 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
40 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
41
42 /* Watchdog init */
43 writel(0xA5A5A500, &rwdt->rwtcsra);
44 writel(0xA5A5A500, &swdt->swtcsra);
45
46 /* CPU frequency setting. Set to 1.4GHz */
47 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
48 u32 stat = 0;
49 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
50 << PLL0_STC_BIT;
51 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
52
53 do {
54 stat = readl(PLLECR) & PLL0ST;
55 } while (stat == 0x0);
56 }
57
58 /* QoS(Quality-of-Service) Init */
59 qos_init();
60 }
61
62 #define TMU0_MSTP125 BIT(25)
63
64 #define SD2CKCR 0xE6150078
65 #define SD2_97500KHZ 0x7
66
board_early_init_f(void)67 int board_early_init_f(void)
68 {
69 /* TMU0 */
70 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
71
72 /*
73 * SD0 clock is set to 97.5MHz by default.
74 * Set SD2 to the 97.5MHz as well.
75 */
76 writel(SD2_97500KHZ, SD2CKCR);
77
78 return 0;
79 }
80
81 #define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
82
board_init(void)83 int board_init(void)
84 {
85 /* adress of boot parameters */
86 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
87
88 cpld_init();
89
90 /* Force ethernet PHY out of reset */
91 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
92 gpio_direction_output(ETHERNET_PHY_RESET, 0);
93 mdelay(20);
94 gpio_direction_output(ETHERNET_PHY_RESET, 1);
95
96 return 0;
97 }
98
dram_init(void)99 int dram_init(void)
100 {
101 if (fdtdec_setup_mem_size_base() != 0)
102 return -EINVAL;
103
104 return 0;
105 }
106
dram_init_banksize(void)107 int dram_init_banksize(void)
108 {
109 fdtdec_setup_memory_banksize();
110
111 return 0;
112 }
113
114 /* Stout has KSZ8041NL/RNL */
115 #define PHY_CONTROL1 0x1E
116 #define PHY_LED_MODE 0xC000
117 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)118 int board_phy_config(struct phy_device *phydev)
119 {
120 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
121 ret &= ~PHY_LED_MODE;
122 ret |= PHY_LED_MODE_ACK;
123 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
124
125 return 0;
126 }
127
env_get_location(enum env_operation op,int prio)128 enum env_location env_get_location(enum env_operation op, int prio)
129 {
130 const u32 load_magic = 0xb33fc0de;
131
132 /* Block environment access if loaded using JTAG */
133 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
134 (op != ENVOP_INIT))
135 return ENVL_UNKNOWN;
136
137 if (prio)
138 return ENVL_UNKNOWN;
139
140 return ENVL_SPI_FLASH;
141 }
142