Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_DDR_TIMING_1 (Results 1 – 25 of 58) sorted by relevance

123

/external/u-boot/include/configs/
DMPC8349EMDS.h80 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 macro
93 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro
DMPC8349EMDS_SDRAM.h80 #define CONFIG_SYS_DDR_TIMING_1 0x38357322 macro
93 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro
Dsocrates.h83 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 macro
Dmpc8308_p1m.h74 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
Dsbc8349.h69 #define CONFIG_SYS_DDR_TIMING_1 0x36332321 macro
DMPC8308RDB.h70 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
DMPC832XEMDS.h49 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
Dve8313.h62 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
DMPC8323ERDB.h49 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
DMPC8540ADS.h86 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 macro
Dids8313.h69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ macro
DMPC8313ERDB_NOR.h85 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ macro
/external/u-boot/board/freescale/mpc8349emds/
Dmpc8349emds.c104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
/external/u-boot/include/configs/km/
Dkm-mpc8360.h63 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ macro
Dkm-mpc832x.h66 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ macro
Dkm-mpc8309.h101 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ macro
/external/u-boot/board/freescale/p1_twr/
Dddr.c33 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()
/external/u-boot/board/socrates/
Dsdram.c38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
/external/u-boot/board/mpc8308_p1m/
Dsdram.c44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
/external/u-boot/board/freescale/mpc8308rdb/
Dsdram.c48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
/external/u-boot/board/gdsys/mpc8308/
Dsdram.c51 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
/external/u-boot/board/freescale/mpc8315erdb/
Dsdram.c65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
/external/u-boot/board/freescale/mpc832xemds/
Dmpc832xemds.c138 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
/external/u-boot/board/freescale/mpc8313erdb/
Dsdram.c74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
/external/u-boot/board/Arcturus/ucp1020/
Dddr.c93 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()

123