1 /* 2 * High Level Configuration Options 3 */ 4 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 5 6 /* 7 * System Clock Setup 8 */ 9 #define CONFIG_83XX_CLKIN 66000000 10 #define CONFIG_SYS_CLK_FREQ 66000000 11 #define CONFIG_83XX_PCICLK 66000000 12 13 /* 14 * QE UEC ethernet configuration 15 */ 16 #define CONFIG_UEC_ETH1 /* GETH1 */ 17 #define UEC_VERBOSE_DEBUG 1 18 19 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 20 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 21 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 22 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 23 #define CONFIG_SYS_UEC1_PHY_ADDR 0 24 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 25 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 26 27 /* 28 * System IO Config 29 */ 30 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 31 32 #define CONFIG_SYS_DDRCDR (\ 33 DDRCDR_EN | \ 34 DDRCDR_PZ_MAXZ | \ 35 DDRCDR_NZ_MAXZ | \ 36 DDRCDR_M_ODR) 37 38 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 39 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 40 SDRAM_CFG_32_BE | \ 41 SDRAM_CFG_SREN | \ 42 SDRAM_CFG_HSE) 43 44 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 45 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 46 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 47 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 48 49 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 50 CSCONFIG_ODT_WR_CFG | \ 51 CSCONFIG_ROW_BIT_13 | \ 52 CSCONFIG_COL_BIT_10) 53 54 #define CONFIG_SYS_DDR_MODE 0x47860242 55 #define CONFIG_SYS_DDR_MODE2 0x8080c000 56 57 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 58 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 59 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 60 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 61 (0 << TIMING_CFG0_WWT_SHIFT) | \ 62 (0 << TIMING_CFG0_RRT_SHIFT) | \ 63 (0 << TIMING_CFG0_WRT_SHIFT) | \ 64 (0 << TIMING_CFG0_RWT_SHIFT)) 65 66 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 67 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 68 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 69 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 70 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 71 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 72 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 73 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 74 75 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 76 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 77 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 78 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 79 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 80 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 81 (5 << TIMING_CFG2_CPO_SHIFT)) 82 83 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 84 85 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 86 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 87 88 /* EEprom support */ 89 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 90 91