Searched refs:CONFIG_SYS_DDR_TIMING_4 (Results 1 – 18 of 18) sorted by relevance
| /external/u-boot/board/freescale/corenet_ds/ |
| D | p4080ds_ddr.c | 66 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
101 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
133 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
165 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
197 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
229 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
261 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
293 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
325 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /external/u-boot/include/configs/ |
| D | BSC9132QDS.h | 166 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
172 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 macro
178 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 macro
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| D | BSC9131RDB.h | 95 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
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| D | p1_twr.h | 95 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| D | MPC8569MDS.h | 100 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| D | UCP1020.h | 219 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| D | P1022DS.h | 152 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| D | P1010RDB.h | 226 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 macro
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| D | p1_p2_rdb_pc.h | 290 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 macro
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| /external/u-boot/board/freescale/bsc9132qds/ |
| D | ddr.c | 36 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
63 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /external/u-boot/board/freescale/p1010rdb/ |
| D | ddr.c | 39 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
66 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /external/u-boot/board/freescale/p1_twr/ |
| D | ddr.c | 45 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /external/u-boot/board/freescale/bsc9131rdb/ |
| D | spl_minimal.c | 45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); in sdram_init()
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| D | ddr.c | 37 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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| /external/u-boot/board/Arcturus/ucp1020/ |
| D | ddr.c | 105 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /external/u-boot/board/freescale/p1_p2_rdb_pc/ |
| D | ddr.c | 237 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, in fixed_sdram()
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| /external/u-boot/board/freescale/mpc8569mds/ |
| D | mpc8569mds.c | 252 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
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| /external/u-boot/scripts/ |
| D | config_whitelist.txt | 2219 CONFIG_SYS_DDR_TIMING_4
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