1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2019 Arcturus Networks, Inc. 4 * https://www.arcturusnetworks.com/products/ucp1020/ 5 * based on include/configs/p1_p2_rdb_pc.h 6 * original copyright follows: 7 * Copyright 2009-2011 Freescale Semiconductor, Inc. 8 */ 9 10 /* 11 * QorIQ uCP1020-xx boards configuration file 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /*** Arcturus FirmWare Environment */ 17 18 #define MAX_SERIAL_SIZE 15 19 #define MAX_HWADDR_SIZE 17 20 21 #define MAX_FWENV_ADDR 4 22 23 #define FWENV_MMC 1 24 #define FWENV_SPI_FLASH 2 25 #define FWENV_NOR_FLASH 3 26 /* 27 #define FWENV_TYPE FWENV_MMC 28 #define FWENV_TYPE FWENV_SPI_FLASH 29 */ 30 #define FWENV_TYPE FWENV_NOR_FLASH 31 32 #if (FWENV_TYPE == FWENV_MMC) 33 #ifndef CONFIG_SYS_MMC_ENV_DEV 34 #define CONFIG_SYS_MMC_ENV_DEV 1 35 #endif 36 #define FWENV_ADDR1 -1 37 #define FWENV_ADDR2 -1 38 #define FWENV_ADDR3 -1 39 #define FWENV_ADDR4 -1 40 #define EMPY_CHAR 0 41 #endif 42 43 #if (FWENV_TYPE == FWENV_SPI_FLASH) 44 #ifndef CONFIG_SF_DEFAULT_SPEED 45 #define CONFIG_SF_DEFAULT_SPEED 1000000 46 #endif 47 #ifndef CONFIG_SF_DEFAULT_MODE 48 #define CONFIG_SF_DEFAULT_MODE SPI_MODE0 49 #endif 50 #ifndef CONFIG_SF_DEFAULT_CS 51 #define CONFIG_SF_DEFAULT_CS 0 52 #endif 53 #ifndef CONFIG_SF_DEFAULT_BUS 54 #define CONFIG_SF_DEFAULT_BUS 0 55 #endif 56 #define FWENV_ADDR1 (0x200 - sizeof(smac)) 57 #define FWENV_ADDR2 (0x400 - sizeof(smac)) 58 #define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) 59 #define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) 60 #define EMPY_CHAR 0xff 61 #endif 62 63 #if (FWENV_TYPE == FWENV_NOR_FLASH) 64 #define FWENV_ADDR1 0xEC080000 65 #define FWENV_ADDR2 -1 66 #define FWENV_ADDR3 -1 67 #define FWENV_ADDR4 -1 68 #define EMPY_CHAR 0xff 69 #endif 70 /***********************************/ 71 72 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 73 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 74 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 75 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 76 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 77 78 #if defined(CONFIG_TARTGET_UCP1020T1) 79 80 #define CONFIG_UCP1020_REV_1_3 81 82 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 83 84 #define CONFIG_TSEC1 85 #define CONFIG_TSEC3 86 #define CONFIG_HAS_ETH0 87 #define CONFIG_HAS_ETH1 88 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 89 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 90 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 91 #define CONFIG_IPADDR 10.80.41.229 92 #define CONFIG_SERVERIP 10.80.41.227 93 #define CONFIG_NETMASK 255.255.252.0 94 #define CONFIG_ETHPRIME "eTSEC3" 95 96 #define CONFIG_SYS_L2_SIZE (256 << 10) 97 98 #endif 99 100 #if defined(CONFIG_TARGET_UCP1020) 101 102 #define CONFIG_UCP1020 103 #define CONFIG_UCP1020_REV_1_3 104 105 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 106 107 #define CONFIG_TSEC1 108 #define CONFIG_TSEC3 109 #define CONFIG_HAS_ETH0 110 #define CONFIG_HAS_ETH1 111 #define CONFIG_HAS_ETH2 112 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 113 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 114 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 115 #define CONFIG_IPADDR 192.168.1.81 116 #define CONFIG_IPADDR1 192.168.1.82 117 #define CONFIG_IPADDR2 192.168.1.83 118 #define CONFIG_SERVERIP 192.168.1.80 119 #define CONFIG_GATEWAYIP 102.168.1.1 120 #define CONFIG_NETMASK 255.255.255.0 121 #define CONFIG_ETHPRIME "eTSEC1" 122 123 #define CONFIG_SYS_L2_SIZE (256 << 10) 124 125 #endif 126 127 #ifdef CONFIG_SDCARD 128 #define CONFIG_RAMBOOT_SDCARD 129 #define CONFIG_SYS_RAMBOOT 130 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 131 #endif 132 133 #ifdef CONFIG_SPIFLASH 134 #define CONFIG_RAMBOOT_SPIFLASH 135 #define CONFIG_SYS_RAMBOOT 136 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 137 #endif 138 139 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 140 141 #ifndef CONFIG_RESET_VECTOR_ADDRESS 142 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 143 #endif 144 145 #ifndef CONFIG_SYS_MONITOR_BASE 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 147 #endif 148 149 #define CONFIG_ENV_OVERWRITE 150 151 #define CONFIG_SYS_SATA_MAX_DEVICE 2 152 #define CONFIG_LBA48 153 154 #define CONFIG_SYS_CLK_FREQ 66666666 155 #define CONFIG_DDR_CLK_FREQ 66666666 156 157 #define CONFIG_HWCONFIG 158 159 /* 160 * These can be toggled for performance analysis, otherwise use default. 161 */ 162 #define CONFIG_L2_CACHE 163 #define CONFIG_BTB 164 165 #define CONFIG_ENABLE_36BIT_PHYS 166 167 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 168 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 169 170 #define CONFIG_SYS_CCSRBAR 0xffe00000 171 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 172 173 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 174 SPL code*/ 175 #ifdef CONFIG_SPL_BUILD 176 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 177 #endif 178 179 /* DDR Setup */ 180 #define CONFIG_DDR_ECC_ENABLE 181 #ifndef CONFIG_DDR_ECC_ENABLE 182 #define CONFIG_SYS_DDR_RAW_TIMING 183 #define CONFIG_DDR_SPD 184 #endif 185 #define CONFIG_SYS_SPD_BUS_NUM 1 186 187 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 188 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 189 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 190 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 191 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 192 193 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 194 195 /* Default settings for DDR3 */ 196 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 197 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 198 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 199 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 200 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 201 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 202 203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 204 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 206 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 207 208 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 209 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 210 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 211 #define CONFIG_SYS_DDR_RCW_1 0x00000000 212 #define CONFIG_SYS_DDR_RCW_2 0x00000000 213 #ifdef CONFIG_DDR_ECC_ENABLE 214 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 215 #else 216 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 217 #endif 218 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 219 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 220 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 221 222 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 223 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 224 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 225 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 226 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 227 #define CONFIG_SYS_DDR_MODE_1 0x40461520 228 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 229 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 230 231 #undef CONFIG_CLOCKS_IN_MHZ 232 233 /* 234 * Memory map 235 * 236 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 237 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 238 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 239 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 240 * (early boot only) 241 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 242 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 243 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 244 */ 245 246 /* 247 * Local Bus Definitions 248 */ 249 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 250 #define CONFIG_SYS_FLASH_BASE 0xec000000 251 252 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 253 254 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 255 | BR_PS_16 | BR_V) 256 257 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 258 259 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 263 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 264 265 #undef CONFIG_SYS_FLASH_CHECKSUM 266 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 267 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 268 269 #define CONFIG_SYS_FLASH_EMPTY_INFO 270 271 #define CONFIG_SYS_INIT_RAM_LOCK 272 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 273 /* Initial L1 address */ 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 277 /* Size of used area in RAM */ 278 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 279 280 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 281 GENERATED_GBL_DATA_SIZE) 282 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 283 284 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 285 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 286 287 #define CONFIG_SYS_PMC_BASE 0xff980000 288 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 289 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 290 BR_PS_8 | BR_V) 291 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 292 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 293 OR_GPCM_EAD) 294 295 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 296 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 297 #ifdef CONFIG_NAND_FSL_ELBC 298 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 299 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 300 #endif 301 302 /* Serial Port - controlled on board with jumper J8 303 * open - index 2 304 * shorted - index 1 305 */ 306 #undef CONFIG_SERIAL_SOFTWARE_FIFO 307 #define CONFIG_SYS_NS16550_SERIAL 308 #define CONFIG_SYS_NS16550_REG_SIZE 1 309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 310 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 311 #define CONFIG_NS16550_MIN_FUNCTIONS 312 #endif 313 314 #define CONFIG_SYS_BAUDRATE_TABLE \ 315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 316 317 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 318 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 319 320 /* I2C */ 321 #define CONFIG_SYS_I2C 322 #define CONFIG_SYS_I2C_FSL 323 #define CONFIG_SYS_FSL_I2C_SPEED 400000 324 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 325 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 326 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 327 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 328 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 329 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 330 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 331 332 #define CONFIG_RTC_DS1337 333 #define CONFIG_RTC_DS1337_NOOSC 334 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 335 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 336 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 337 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 338 339 #if defined(CONFIG_PCI) 340 /* 341 * General PCI 342 * Memory space is mapped 1-1, but I/O space must start from 0. 343 */ 344 345 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 346 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 347 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 348 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 349 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 350 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 351 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 352 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 353 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 354 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 355 356 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 357 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 358 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 359 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 360 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 361 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 362 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 363 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 364 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 365 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 366 367 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 368 #endif /* CONFIG_PCI */ 369 370 /* 371 * Environment 372 */ 373 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD) 374 #define CONFIG_FSL_FIXED_MMC_LOCATION 375 #define CONFIG_SYS_MMC_ENV_DEV 0 376 #endif 377 378 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 379 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 380 381 /* 382 * USB 383 */ 384 #define CONFIG_HAS_FSL_DR_USB 385 386 #if defined(CONFIG_HAS_FSL_DR_USB) 387 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 388 389 #ifdef CONFIG_USB_EHCI_HCD 390 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 391 #define CONFIG_USB_EHCI_FSL 392 #endif 393 #endif 394 395 #undef CONFIG_WATCHDOG /* watchdog disabled */ 396 397 #ifdef CONFIG_MMC 398 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 399 #endif 400 401 /* Misc Extra Settings */ 402 #undef CONFIG_WATCHDOG /* watchdog disabled */ 403 404 /* 405 * Miscellaneous configurable options 406 */ 407 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 408 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 409 410 /* 411 * For booting Linux, the board info and command line data 412 * have to be in the first 64 MB of memory, since this is 413 * the maximum mapped by the Linux kernel during initialization. 414 */ 415 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 416 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 417 418 #if defined(CONFIG_CMD_KGDB) 419 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 420 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 421 #endif 422 423 /* 424 * Environment Configuration 425 */ 426 427 #if defined(CONFIG_TSEC_ENET) 428 429 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) 430 #else 431 #error "UCP1020 module revision is not defined !!!" 432 #endif 433 434 #define CONFIG_BOOTP_SERVERIP 435 436 #define CONFIG_TSEC1_NAME "eTSEC1" 437 #define CONFIG_TSEC2_NAME "eTSEC2" 438 #define CONFIG_TSEC3_NAME "eTSEC3" 439 440 #define TSEC1_PHY_ADDR 4 441 #define TSEC2_PHY_ADDR 0 442 #define TSEC2_PHY_ADDR_SGMII 0x00 443 #define TSEC3_PHY_ADDR 6 444 445 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 446 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 447 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 448 449 #define TSEC1_PHYIDX 0 450 #define TSEC2_PHYIDX 0 451 #define TSEC3_PHYIDX 0 452 453 #endif 454 455 #define CONFIG_HOSTNAME "UCP1020" 456 #define CONFIG_ROOTPATH "/opt/nfsroot" 457 #define CONFIG_BOOTFILE "uImage" 458 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 459 460 /* default location for tftp and bootm */ 461 #define CONFIG_LOADADDR 1000000 462 463 #if defined(CONFIG_DONGLE) 464 465 #define CONFIG_EXTRA_ENV_SETTINGS \ 466 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 467 "bootfile=uImage\0" \ 468 "consoledev=ttyS0\0" \ 469 "cramfsfile=image.cramfs\0" \ 470 "dtbaddr=0x00c00000\0" \ 471 "dtbfile=image.dtb\0" \ 472 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 473 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 474 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 475 "fileaddr=0x01000000\0" \ 476 "filesize=0x00080000\0" \ 477 "flashmbr=sf probe 0; " \ 478 "tftp $loadaddr $mbr; " \ 479 "sf erase $mbr_offset +$filesize; " \ 480 "sf write $loadaddr $mbr_offset $filesize\0" \ 481 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 482 "protect off $nor_recoveryaddr +$filesize; " \ 483 "erase $nor_recoveryaddr +$filesize; " \ 484 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 485 "protect on $nor_recoveryaddr +$filesize\0 " \ 486 "flashuboot=tftp $ubootaddr $ubootfile; " \ 487 "protect off $nor_ubootaddr +$filesize; " \ 488 "erase $nor_ubootaddr +$filesize; " \ 489 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 490 "protect on $nor_ubootaddr +$filesize\0 " \ 491 "flashworking=tftp $workingaddr $cramfsfile; " \ 492 "protect off $nor_workingaddr +$filesize; " \ 493 "erase $nor_workingaddr +$filesize; " \ 494 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 495 "protect on $nor_workingaddr +$filesize\0 " \ 496 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 497 "kerneladdr=0x01100000\0" \ 498 "kernelfile=uImage\0" \ 499 "loadaddr=0x01000000\0" \ 500 "mbr=uCP1020d.mbr\0" \ 501 "mbr_offset=0x00000000\0" \ 502 "mmbr=uCP1020Quiet.mbr\0" \ 503 "mmcpart=0:2\0" \ 504 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 505 "mmc erase 1 1; " \ 506 "mmc write $loadaddr 1 1\0" \ 507 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 508 "mmc erase 0x40 0x400; " \ 509 "mmc write $loadaddr 0x40 0x400\0" \ 510 "netdev=eth0\0" \ 511 "nor_recoveryaddr=0xEC0A0000\0" \ 512 "nor_ubootaddr=0xEFF80000\0" \ 513 "nor_workingaddr=0xECFA0000\0" \ 514 "norbootrecovery=setenv bootargs $recoverybootargs" \ 515 " console=$consoledev,$baudrate $othbootargs; " \ 516 "run norloadrecovery; " \ 517 "bootm $kerneladdr - $dtbaddr\0" \ 518 "norbootworking=setenv bootargs $workingbootargs" \ 519 " console=$consoledev,$baudrate $othbootargs; " \ 520 "run norloadworking; " \ 521 "bootm $kerneladdr - $dtbaddr\0" \ 522 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 523 "setenv cramfsaddr $nor_recoveryaddr; " \ 524 "cramfsload $dtbaddr $dtbfile; " \ 525 "cramfsload $kerneladdr $kernelfile\0" \ 526 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 527 "setenv cramfsaddr $nor_workingaddr; " \ 528 "cramfsload $dtbaddr $dtbfile; " \ 529 "cramfsload $kerneladdr $kernelfile\0" \ 530 "prog_spi_mbr=run spi__mbr\0" \ 531 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 532 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 533 "run spi__cramfs\0" \ 534 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 535 " console=$consoledev,$baudrate $othbootargs; " \ 536 "tftp $rootfsaddr $rootfsfile; " \ 537 "tftp $loadaddr $kernelfile; " \ 538 "tftp $dtbaddr $dtbfile; " \ 539 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 540 "ramdisk_size=120000\0" \ 541 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 542 "recoveryaddr=0x02F00000\0" \ 543 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 544 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 545 "mw.l 0xffe0f008 0x00400000\0" \ 546 "rootfsaddr=0x02F00000\0" \ 547 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 548 "rootpath=/opt/nfsroot\0" \ 549 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 550 "protect off 0xeC000000 +$filesize; " \ 551 "erase 0xEC000000 +$filesize; " \ 552 "cp.b $loadaddr 0xEC000000 $filesize; " \ 553 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 554 "protect on 0xeC000000 +$filesize\0" \ 555 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 556 "protect off 0xeFF80000 +$filesize; " \ 557 "erase 0xEFF80000 +$filesize; " \ 558 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 559 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 560 "protect on 0xeFF80000 +$filesize\0" \ 561 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 562 "sf probe 0; sf erase 0x8000 +$filesize; " \ 563 "sf write $loadaddr 0x8000 $filesize\0" \ 564 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 565 "protect off 0xec0a0000 +$filesize; " \ 566 "erase 0xeC0A0000 +$filesize; " \ 567 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 568 "protect on 0xec0a0000 +$filesize\0" \ 569 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 570 "sf probe 1; sf erase 0 +$filesize; " \ 571 "sf write $loadaddr 0 $filesize\0" \ 572 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 573 "sf probe 0; sf erase 0 +$filesize; " \ 574 "sf write $loadaddr 0 $filesize\0" \ 575 "tftpflash=tftpboot $loadaddr $uboot; " \ 576 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 577 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 578 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 579 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 580 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 581 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 582 "ubootaddr=0x01000000\0" \ 583 "ubootfile=u-boot.bin\0" \ 584 "ubootd=u-boot4dongle.bin\0" \ 585 "upgrade=run flashworking\0" \ 586 "usb_phy_type=ulpi\0 " \ 587 "workingaddr=0x02F00000\0" \ 588 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 589 590 #else 591 592 #if defined(CONFIG_UCP1020T1) 593 594 #define CONFIG_EXTRA_ENV_SETTINGS \ 595 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 596 "bootfile=uImage\0" \ 597 "consoledev=ttyS0\0" \ 598 "cramfsfile=image.cramfs\0" \ 599 "dtbaddr=0x00c00000\0" \ 600 "dtbfile=image.dtb\0" \ 601 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 602 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 603 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 604 "fileaddr=0x01000000\0" \ 605 "filesize=0x00080000\0" \ 606 "flashmbr=sf probe 0; " \ 607 "tftp $loadaddr $mbr; " \ 608 "sf erase $mbr_offset +$filesize; " \ 609 "sf write $loadaddr $mbr_offset $filesize\0" \ 610 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 611 "protect off $nor_recoveryaddr +$filesize; " \ 612 "erase $nor_recoveryaddr +$filesize; " \ 613 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 614 "protect on $nor_recoveryaddr +$filesize\0 " \ 615 "flashuboot=tftp $ubootaddr $ubootfile; " \ 616 "protect off $nor_ubootaddr +$filesize; " \ 617 "erase $nor_ubootaddr +$filesize; " \ 618 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 619 "protect on $nor_ubootaddr +$filesize\0 " \ 620 "flashworking=tftp $workingaddr $cramfsfile; " \ 621 "protect off $nor_workingaddr +$filesize; " \ 622 "erase $nor_workingaddr +$filesize; " \ 623 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 624 "protect on $nor_workingaddr +$filesize\0 " \ 625 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 626 "kerneladdr=0x01100000\0" \ 627 "kernelfile=uImage\0" \ 628 "loadaddr=0x01000000\0" \ 629 "mbr=uCP1020.mbr\0" \ 630 "mbr_offset=0x00000000\0" \ 631 "netdev=eth0\0" \ 632 "nor_recoveryaddr=0xEC0A0000\0" \ 633 "nor_ubootaddr=0xEFF80000\0" \ 634 "nor_workingaddr=0xECFA0000\0" \ 635 "norbootrecovery=setenv bootargs $recoverybootargs" \ 636 " console=$consoledev,$baudrate $othbootargs; " \ 637 "run norloadrecovery; " \ 638 "bootm $kerneladdr - $dtbaddr\0" \ 639 "norbootworking=setenv bootargs $workingbootargs" \ 640 " console=$consoledev,$baudrate $othbootargs; " \ 641 "run norloadworking; " \ 642 "bootm $kerneladdr - $dtbaddr\0" \ 643 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 644 "setenv cramfsaddr $nor_recoveryaddr; " \ 645 "cramfsload $dtbaddr $dtbfile; " \ 646 "cramfsload $kerneladdr $kernelfile\0" \ 647 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 648 "setenv cramfsaddr $nor_workingaddr; " \ 649 "cramfsload $dtbaddr $dtbfile; " \ 650 "cramfsload $kerneladdr $kernelfile\0" \ 651 "othbootargs=quiet\0" \ 652 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 653 " console=$consoledev,$baudrate $othbootargs; " \ 654 "tftp $rootfsaddr $rootfsfile; " \ 655 "tftp $loadaddr $kernelfile; " \ 656 "tftp $dtbaddr $dtbfile; " \ 657 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 658 "ramdisk_size=120000\0" \ 659 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 660 "recoveryaddr=0x02F00000\0" \ 661 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 662 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 663 "mw.l 0xffe0f008 0x00400000\0" \ 664 "rootfsaddr=0x02F00000\0" \ 665 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 666 "rootpath=/opt/nfsroot\0" \ 667 "silent=1\0" \ 668 "tftpflash=tftpboot $loadaddr $uboot; " \ 669 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 670 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 671 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 672 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 673 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 674 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 675 "ubootaddr=0x01000000\0" \ 676 "ubootfile=u-boot.bin\0" \ 677 "upgrade=run flashworking\0" \ 678 "workingaddr=0x02F00000\0" \ 679 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 680 681 #else /* For Arcturus Modules */ 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "bootcmd=run norkernel\0" \ 685 "bootfile=uImage\0" \ 686 "consoledev=ttyS0\0" \ 687 "dtbaddr=0x00c00000\0" \ 688 "dtbfile=image.dtb\0" \ 689 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 690 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 691 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 692 "fileaddr=0x01000000\0" \ 693 "filesize=0x00080000\0" \ 694 "flashmbr=sf probe 0; " \ 695 "tftp $loadaddr $mbr; " \ 696 "sf erase $mbr_offset +$filesize; " \ 697 "sf write $loadaddr $mbr_offset $filesize\0" \ 698 "flashuboot=tftp $loadaddr $ubootfile; " \ 699 "protect off $nor_ubootaddr0 +$filesize; " \ 700 "erase $nor_ubootaddr0 +$filesize; " \ 701 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 702 "protect on $nor_ubootaddr0 +$filesize; " \ 703 "protect off $nor_ubootaddr1 +$filesize; " \ 704 "erase $nor_ubootaddr1 +$filesize; " \ 705 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 706 "protect on $nor_ubootaddr1 +$filesize\0 " \ 707 "format0=protect off $part0base +$part0size; " \ 708 "erase $part0base +$part0size\0" \ 709 "format1=protect off $part1base +$part1size; " \ 710 "erase $part1base +$part1size\0" \ 711 "format2=protect off $part2base +$part2size; " \ 712 "erase $part2base +$part2size\0" \ 713 "format3=protect off $part3base +$part3size; " \ 714 "erase $part3base +$part3size\0" \ 715 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 716 "kerneladdr=0x01100000\0" \ 717 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 718 "kernelfile=uImage\0" \ 719 "loadaddr=0x01000000\0" \ 720 "mbr=uCP1020.mbr\0" \ 721 "mbr_offset=0x00000000\0" \ 722 "netdev=eth0\0" \ 723 "nor_ubootaddr0=0xEC000000\0" \ 724 "nor_ubootaddr1=0xEFF80000\0" \ 725 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 726 "run norkernelload; " \ 727 "bootm $kerneladdr - $dtbaddr\0" \ 728 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 729 "setenv cramfsaddr $part0base; " \ 730 "cramfsload $dtbaddr $dtbfile; " \ 731 "cramfsload $kerneladdr $kernelfile\0" \ 732 "part0base=0xEC100000\0" \ 733 "part0size=0x00700000\0" \ 734 "part1base=0xEC800000\0" \ 735 "part1size=0x02000000\0" \ 736 "part2base=0xEE800000\0" \ 737 "part2size=0x00800000\0" \ 738 "part3base=0xEF000000\0" \ 739 "part3size=0x00F80000\0" \ 740 "partENVbase=0xEC080000\0" \ 741 "partENVsize=0x00080000\0" \ 742 "program0=tftp part0-000000.bin; " \ 743 "protect off $part0base +$filesize; " \ 744 "erase $part0base +$filesize; " \ 745 "cp.b $loadaddr $part0base $filesize; " \ 746 "echo Verifying...; " \ 747 "cmp.b $loadaddr $part0base $filesize\0" \ 748 "program1=tftp part1-000000.bin; " \ 749 "protect off $part1base +$filesize; " \ 750 "erase $part1base +$filesize; " \ 751 "cp.b $loadaddr $part1base $filesize; " \ 752 "echo Verifying...; " \ 753 "cmp.b $loadaddr $part1base $filesize\0" \ 754 "program2=tftp part2-000000.bin; " \ 755 "protect off $part2base +$filesize; " \ 756 "erase $part2base +$filesize; " \ 757 "cp.b $loadaddr $part2base $filesize; " \ 758 "echo Verifying...; " \ 759 "cmp.b $loadaddr $part2base $filesize\0" \ 760 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 761 " console=$consoledev,$baudrate $othbootargs; " \ 762 "tftp $rootfsaddr $rootfsfile; " \ 763 "tftp $loadaddr $kernelfile; " \ 764 "tftp $dtbaddr $dtbfile; " \ 765 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 766 "ramdisk_size=120000\0" \ 767 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 768 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 769 "mw.l 0xffe0f008 0x00400000\0" \ 770 "rootfsaddr=0x02F00000\0" \ 771 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 772 "rootpath=/opt/nfsroot\0" \ 773 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 774 "sf probe 0; sf erase 0 +$filesize; " \ 775 "sf write $loadaddr 0 $filesize\0" \ 776 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 777 "protect off 0xeC000000 +$filesize; " \ 778 "erase 0xEC000000 +$filesize; " \ 779 "cp.b $loadaddr 0xEC000000 $filesize; " \ 780 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 781 "protect on 0xeC000000 +$filesize\0" \ 782 "tftpflash=tftpboot $loadaddr $uboot; " \ 783 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 784 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 785 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 786 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 787 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 788 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 789 "ubootfile=u-boot.bin\0" \ 790 "upgrade=run flashuboot\0" \ 791 "usb_phy_type=ulpi\0 " \ 792 "boot_nfs= " \ 793 "setenv bootargs root=/dev/nfs rw " \ 794 "nfsroot=$serverip:$rootpath " \ 795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $loadaddr $bootfile;" \ 798 "tftp $fdtaddr $fdtfile;" \ 799 "bootm $loadaddr - $fdtaddr\0" \ 800 "boot_hd = " \ 801 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "usb start;" \ 804 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 805 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 806 "bootm $loadaddr - $fdtaddr\0" \ 807 "boot_usb_fat = " \ 808 "setenv bootargs root=/dev/ram rw " \ 809 "console=$consoledev,$baudrate $othbootargs " \ 810 "ramdisk_size=$ramdisk_size;" \ 811 "usb start;" \ 812 "fatload usb 0:2 $loadaddr $bootfile;" \ 813 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 814 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 815 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 816 "boot_usb_ext2 = " \ 817 "setenv bootargs root=/dev/ram rw " \ 818 "console=$consoledev,$baudrate $othbootargs " \ 819 "ramdisk_size=$ramdisk_size;" \ 820 "usb start;" \ 821 "ext2load usb 0:4 $loadaddr $bootfile;" \ 822 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 823 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 824 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 825 "boot_nor = " \ 826 "setenv bootargs root=/dev/$jffs2nor rw " \ 827 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 828 "bootm $norbootaddr - $norfdtaddr\0 " \ 829 "boot_ram = " \ 830 "setenv bootargs root=/dev/ram rw " \ 831 "console=$consoledev,$baudrate $othbootargs " \ 832 "ramdisk_size=$ramdisk_size;" \ 833 "tftp $ramdiskaddr $ramdiskfile;" \ 834 "tftp $loadaddr $bootfile;" \ 835 "tftp $fdtaddr $fdtfile;" \ 836 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 837 838 #endif 839 #endif 840 841 #endif /* __CONFIG_H */ 842