Searched refs:CONFIG_SYS_DDR_TIMING_5 (Results 1 – 18 of 18) sorted by relevance
| /external/u-boot/board/freescale/corenet_ds/ |
| D | p4080ds_ddr.c | 67 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /external/u-boot/include/configs/ |
| D | BSC9132QDS.h | 167 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
173 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 macro
179 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
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| D | BSC9131RDB.h | 96 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
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| D | p1_twr.h | 96 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| D | MPC8569MDS.h | 101 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| D | UCP1020.h | 220 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| D | P1022DS.h | 153 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
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| D | P1010RDB.h | 227 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| D | p1_p2_rdb_pc.h | 291 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
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| /external/u-boot/board/freescale/bsc9132qds/ |
| D | ddr.c | 37 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
64 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /external/u-boot/board/freescale/p1010rdb/ |
| D | ddr.c | 40 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
67 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /external/u-boot/board/freescale/p1_twr/ |
| D | ddr.c | 46 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /external/u-boot/board/freescale/bsc9131rdb/ |
| D | spl_minimal.c | 46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); in sdram_init()
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| D | ddr.c | 38 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /external/u-boot/board/Arcturus/ucp1020/ |
| D | ddr.c | 106 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /external/u-boot/board/freescale/p1_p2_rdb_pc/ |
| D | ddr.c | 238 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /external/u-boot/board/freescale/mpc8569mds/ |
| D | mpc8569mds.c | 253 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); in fixed_sdram()
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| /external/u-boot/scripts/ |
| D | config_whitelist.txt | 2222 CONFIG_SYS_DDR_TIMING_5
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