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Searched refs:CPLD_READ (Results 1 – 23 of 23) sorted by relevance

/external/u-boot/board/freescale/t104xrdb/
Dcpld.c38 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_altbank()
51 u8 reg = CPLD_READ(flash_ctl_status); in cpld_set_defbank()
62 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
63 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
64 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
65 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
66 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
67 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
68 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
69 printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); in cpld_dump_regs()
[all …]
Dt104xrdb.c39 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); in checkboard()
41 sw = CPLD_READ(flash_ctl_status); in checkboard()
101 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
106 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | in misc_init_r()
111 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | in misc_init_r()
114 CPLD_READ(sfp_ctl_status)); in misc_init_r()
117 if (CPLD_READ(sw_ver) < 0x03) { in misc_init_r()
119 CPLD_READ(sw_ver)); in misc_init_r()
Dcpld.h41 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
Ddiu.c71 sw = CPLD_READ(sfp_ctl_status); in platform_diu_init()
/external/u-boot/board/freescale/t4rdb/
Dcpld.c44 val = CPLD_READ(vbank); in cpld_set_altbank()
52 override = CPLD_READ(software_on); in cpld_set_altbank()
77 printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); in cpld_dump_regs()
78 printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); in cpld_dump_regs()
79 printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); in cpld_dump_regs()
80 printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); in cpld_dump_regs()
81 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
82 printf("software_on = 0x%02x\n", CPLD_READ(software_on)); in cpld_dump_regs()
83 printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); in cpld_dump_regs()
84 printf("res0 = 0x%02x\n", CPLD_READ(res0)); in cpld_dump_regs()
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Dt4240rdb.c35 CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); in checkboard()
37 sw = CPLD_READ(vbank); in checkboard()
Dcpld.h45 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/external/u-boot/board/freescale/t102xrdb/
Dcpld.c34 u8 reg = CPLD_READ(flash_csr); in cpld_set_altbank()
47 u8 reg = CPLD_READ(flash_csr); in cpld_set_defbank()
57 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
58 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
59 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); in cpld_dump_regs()
60 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); in cpld_dump_regs()
61 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); in cpld_dump_regs()
62 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); in cpld_dump_regs()
63 printf("int_status = 0x%02x\n", CPLD_READ(int_status)); in cpld_dump_regs()
64 printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); in cpld_dump_regs()
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Dt102xrdb.c57 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); in checkboard()
70 reg = CPLD_READ(flash_csr); in checkboard()
100 u8 reg = CPLD_READ(misc_ctl_status); in board_mux_lane()
Dcpld.h32 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/external/u-boot/board/freescale/ls1046ardb/
Dcpld.c31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank()
34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank()
96 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
97 printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
98 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
99 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); in cpld_dump_regs()
100 printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); in cpld_dump_regs()
101 printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); in cpld_dump_regs()
102 printf("vbank = %x\n", CPLD_READ(vbank)); in cpld_dump_regs()
[all …]
Dls1046ardb.c45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); in checkboard()
46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); in checkboard()
52 printf("QSPI vBank %d\n", CPLD_READ(vbank)); in checkboard()
58 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), in checkboard()
59 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); in checkboard()
62 sd1refclk_sel = CPLD_READ(sd1refclk_sel); in checkboard()
Dcpld.h39 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/external/u-boot/board/freescale/p2041rdb/
Dcpld.c51 u8 reg5 = CPLD_READ(sw_ctl_on); in __cpld_set_altbank()
73 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
74 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
75 printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
76 printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); in cpld_dump_regs()
77 printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); in cpld_dump_regs()
78 printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); in cpld_dump_regs()
79 printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); in cpld_dump_regs()
80 printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); in cpld_dump_regs()
81 printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); in cpld_dump_regs()
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Dp2041rdb.c34 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), in checkboard()
35 CPLD_READ(cpld_ver_sub)); in checkboard()
37 sw = CPLD_READ(fbank_sel); in checkboard()
150 u8 sysclk_conf = CPLD_READ(sysclk_sw1); in get_board_sys_clk()
195 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && in misc_init_r()
196 (CPLD_READ(pcba_ver) == 5)) { in misc_init_r()
Dcpld.h53 #define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) macro
Deth.c50 u8 mux = CPLD_READ(serdes_mux); in initialize_lane_to_slot()
/external/u-boot/board/freescale/ls1043ardb/
Dcpld.c31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank()
34 u8 reg7 = CPLD_READ(vbank); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank()
103 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); in cpld_dump_regs()
104 printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); in cpld_dump_regs()
105 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); in cpld_dump_regs()
106 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); in cpld_dump_regs()
107 printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); in cpld_dump_regs()
108 printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); in cpld_dump_regs()
109 printf("vbank = %x\n", CPLD_READ(vbank)); in cpld_dump_regs()
[all …]
Dls1043ardb.c160 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); in checkboard()
161 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); in checkboard()
167 printf("vBank %d\n", CPLD_READ(vbank)); in checkboard()
177 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), in checkboard()
178 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); in checkboard()
181 sd1refclk_sel = CPLD_READ(sd1refclk_sel); in checkboard()
Dcpld.h34 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro
/external/u-boot/board/freescale/t208xrdb/
Dt208xrdb.c33 CPLD_READ(hw_ver), CPLD_READ(sw_ver)); in checkboard()
42 reg = CPLD_READ(flash_csr); in checkboard()
108 reg = CPLD_READ(reset_ctl); in misc_init_r()
Dcpld.c29 u8 reg = CPLD_READ(flash_csr); in cpld_set_altbank()
39 u8 reg = CPLD_READ(flash_csr); in cpld_set_defbank()
Dcpld.h29 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) macro