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Searched refs:DPLL_MODE_MASK (Results 1 – 16 of 16) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk322x.c182 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, in rkclk_pll_get_rate()
340 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
344 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
Dclk_rk3188.c149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
Dclk_rk3288.c205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
Dclk_rk3036.c181 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, in rkclk_pll_get_rate()
Dclk_rk3128.c250 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, in rkclk_pll_get_rate()
Dclk_px30.c83 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3188.h164 DPLL_MODE_MASK = 3, enumerator
Dcru_rk3036.h93 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
Dcru_rk322x.h100 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
Dcru_rk3128.h102 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator
Dcru_rk3288.h198 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, enumerator
Dcru_px30.h156 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator
/external/u-boot/arch/arm/include/asm/arch-rk3308/
Dcru_rk3308.h135 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c331 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
350 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
/external/igt-gpu-tools/lib/
Dintel_reg.h949 # define DPLL_MODE_MASK (3 << 26) macro
/external/igt-gpu-tools/tools/
Dintel_reg_decode.c539 switch (val & DPLL_MODE_MASK) { in DEBUGSTRING()