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Searched refs:DXnGSR0 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a33.c252 low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; in mctl_channel_init()
253 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; in mctl_channel_init()
Ddram_sun8i_a83t.c344 low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03; in mctl_channel_init()
345 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03; in mctl_channel_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h147 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) macro
Ddram_sun8i_a83t.h152 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) macro