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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Sun8i a33 platform dram controller init.
4  *
5  * (C) Copyright 2007-2015 Allwinner Technology Co.
6  *                         Jerry Wang <wangflord@allwinnertech.com>
7  * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
8  * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
9  */
10 #include <common.h>
11 #include <errno.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/dram.h>
15 #include <asm/arch/prcm.h>
16 
17 /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
18 #define DRAM_CLK_MUL 2
19 #define DRAM_CLK_DIV 4
20 #define DRAM_SIGMA_DELTA_ENABLE 1
21 
22 struct dram_para {
23 	u8 cs1;
24 	u8 seq;
25 	u8 bank;
26 	u8 rank;
27 	u8 rows;
28 	u8 bus_width;
29 	u16 page_size;
30 };
31 
mctl_set_cr(struct dram_para * para)32 static void mctl_set_cr(struct dram_para *para)
33 {
34 	struct sunxi_mctl_com_reg * const mctl_com =
35 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
36 
37 	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
38 	       MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
39 	       (para->seq ? MCTL_CR_SEQUENCE : 0) |
40 	       ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
41 	       MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
42 	       MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
43 	       &mctl_com->cr);
44 }
45 
auto_detect_dram_size(struct dram_para * para)46 static void auto_detect_dram_size(struct dram_para *para)
47 {
48 	u8 orig_rank = para->rank;
49 	int rows, columns;
50 
51 	/* Row detect */
52 	para->page_size = 512;
53 	para->seq = 1;
54 	para->rows = 16;
55 	para->rank = 1;
56 	mctl_set_cr(para);
57 	for (rows = 11 ; rows < 16 ; rows++) {
58 		if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
59 			break;
60 	}
61 
62 	/* Column (page size) detect */
63 	para->rows = 11;
64 	para->page_size = 8192;
65 	mctl_set_cr(para);
66 	for (columns = 9 ; columns < 13 ; columns++) {
67 		if (mctl_mem_matches(1 << columns))
68 			break;
69 	}
70 
71 	para->seq = 0;
72 	para->rank = orig_rank;
73 	para->rows = rows;
74 	para->page_size = 1 << columns;
75 	mctl_set_cr(para);
76 }
77 
ns_to_t(int nanoseconds)78 static inline int ns_to_t(int nanoseconds)
79 {
80 	const unsigned int ctrl_freq =
81 		CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
82 
83 	return (ctrl_freq * nanoseconds + 999) / 1000;
84 }
85 
auto_set_timing_para(struct dram_para * para)86 static void auto_set_timing_para(struct dram_para *para)
87 {
88 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
89 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
90 	u32 reg_val;
91 
92 	u8 tccd		= 2;
93 	u8 tfaw		= ns_to_t(50);
94 	u8 trrd		= max(ns_to_t(10), 4);
95 	u8 trcd		= ns_to_t(15);
96 	u8 trc		= ns_to_t(53);
97 	u8 txp		= max(ns_to_t(8), 3);
98 	u8 twtr		= max(ns_to_t(8), 4);
99 	u8 trtp		= max(ns_to_t(8), 4);
100 	u8 twr		= max(ns_to_t(15), 3);
101 	u8 trp		= ns_to_t(15);
102 	u8 tras		= ns_to_t(38);
103 
104 	u16 trefi	= ns_to_t(7800) / 32;
105 	u16 trfc	= ns_to_t(350);
106 
107 	/* Fixed timing parameters */
108 	u8 tmrw		= 0;
109 	u8 tmrd		= 4;
110 	u8 tmod		= 12;
111 	u8 tcke		= 3;
112 	u8 tcksrx	= 5;
113 	u8 tcksre	= 5;
114 	u8 tckesr	= 4;
115 	u8 trasmax	= 24;
116 	u8 tcl		= 6; /* CL 12 */
117 	u8 tcwl		= 4; /* CWL 8 */
118 	u8 t_rdata_en	= 4;
119 	u8 wr_latency	= 2;
120 
121 	u32 tdinit0	= (500 * CONFIG_DRAM_CLK) + 1;		/* 500us */
122 	u32 tdinit1	= (360 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 360ns */
123 	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
124 	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */
125 
126 	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
127 	u8 twr2rd	= tcwl + 2 + twtr; 	/* WL + BL / 2 + tWTR */
128 	u8 trd2wr	= tcl + 2 + 1 - tcwl; 	/* RL + BL / 2 + 2 - WL */
129 
130 	/* Set work mode register */
131 	mctl_set_cr(para);
132 	/* Set mode register */
133 	writel(MCTL_MR0, &mctl_ctl->mr0);
134 	writel(MCTL_MR1, &mctl_ctl->mr1);
135 	writel(MCTL_MR2, &mctl_ctl->mr2);
136 	writel(MCTL_MR3, &mctl_ctl->mr3);
137 	/* Set dram timing */
138 	reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
139 	writel(reg_val, &mctl_ctl->dramtmg0);
140 	reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
141 	writel(reg_val, &mctl_ctl->dramtmg1);
142 	reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
143 	writel(reg_val, &mctl_ctl->dramtmg2);
144 	reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
145 	writel(reg_val, &mctl_ctl->dramtmg3);
146 	reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
147 	writel(reg_val, &mctl_ctl->dramtmg4);
148 	reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
149 	writel(reg_val, &mctl_ctl->dramtmg5);
150 	/* Set two rank timing and exit self-refresh timing */
151 	reg_val = readl(&mctl_ctl->dramtmg8);
152 	reg_val &= ~(0xff << 8);
153 	reg_val &= ~(0xff << 0);
154 	reg_val |= (0x33 << 8);
155 	reg_val |= (0x10 << 0);
156 	writel(reg_val, &mctl_ctl->dramtmg8);
157 	/* Set phy interface time */
158 	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
159 			| (wr_latency << 0);
160 	/* PHY interface write latency and read latency configure */
161 	writel(reg_val, &mctl_ctl->pitmg0);
162 	/* Set phy time  PTR0-2 use default */
163 	writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
164 	writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
165 	/* Set refresh timing */
166 	reg_val = (trefi << 16) | (trfc << 0);
167 	writel(reg_val, &mctl_ctl->rfshtmg);
168 }
169 
mctl_set_pir(u32 val)170 static void mctl_set_pir(u32 val)
171 {
172 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
173 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
174 
175 	writel(val, &mctl_ctl->pir);
176 	mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
177 }
178 
mctl_data_train_cfg(struct dram_para * para)179 static void mctl_data_train_cfg(struct dram_para *para)
180 {
181 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
182 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
183 
184 	if (para->rank == 2)
185 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
186 	else
187 		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
188 }
189 
mctl_train_dram(struct dram_para * para)190 static int mctl_train_dram(struct dram_para *para)
191 {
192 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
193 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
194 
195 	mctl_data_train_cfg(para);
196 	mctl_set_pir(0x5f3);
197 
198 	return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
199 }
200 
mctl_channel_init(struct dram_para * para)201 static int mctl_channel_init(struct dram_para *para)
202 {
203 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
204 		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
205 	struct sunxi_mctl_com_reg * const mctl_com =
206 		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
207 	u32 low_data_lines_status;  /* Training status of datalines 0 - 7 */
208 	u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
209 
210 	auto_set_timing_para(para);
211 
212 	/* Disable dram VTC */
213 	clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
214 
215 	/* Set ODT */
216 	if ((CONFIG_DRAM_CLK > 400) && IS_ENABLED(CONFIG_DRAM_ODT_EN)) {
217 		setbits_le32(DXnGCR0(0), 0x3 << 9);
218 		setbits_le32(DXnGCR0(1), 0x3 << 9);
219 	} else {
220 		clrbits_le32(DXnGCR0(0), 0x3 << 9);
221 		clrbits_le32(DXnGCR0(1), 0x3 << 9);
222 	}
223 
224 	/* set PLL configuration */
225 	if (CONFIG_DRAM_CLK >= 480)
226 		setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
227 	else
228 		setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
229 
230 	/* Auto detect dram config, set 2 rank and 16bit bus-width */
231 	para->cs1 = 0;
232 	para->rank = 2;
233 	para->bus_width = 16;
234 	mctl_set_cr(para);
235 
236 	/* Open DQS gating */
237 	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
238 	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
239 
240 	mctl_data_train_cfg(para);
241 
242 	/* ZQ calibration */
243 	writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
244 	/* CA calibration */
245 	mctl_set_pir(0x00000003);
246 	/* More ZQ calibration */
247 	writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
248 	writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
249 
250 	/* DQS gate training */
251 	if (mctl_train_dram(para) != 0) {
252 		low_data_lines_status  = (readl(DXnGSR0(0)) >> 24) & 0x03;
253 		high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
254 
255 		if (low_data_lines_status == 0x3)
256 			return -EIO;
257 
258 		/* DRAM has only one rank */
259 		para->rank = 1;
260 		mctl_set_cr(para);
261 
262 		if (low_data_lines_status == high_data_lines_status)
263 			goto done; /* 16 bit bus, 1 rank */
264 
265 		if (!(low_data_lines_status & high_data_lines_status)) {
266 			/* Retry 16 bit bus-width with CS1 set */
267 			para->cs1 = 1;
268 			mctl_set_cr(para);
269 			if (mctl_train_dram(para) == 0)
270 				goto done;
271 		}
272 
273 		/* Try 8 bit bus-width */
274 		writel(0x0, DXnGCR0(1)); /* Disable high DQ */
275 		para->cs1 = 0;
276 		para->bus_width = 8;
277 		mctl_set_cr(para);
278 		if (mctl_train_dram(para) != 0)
279 			return -EIO;
280 	}
281 done:
282 	/* Check the dramc status */
283 	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
284 
285 	/* Close DQS gating */
286 	setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
287 
288 	/* Enable master access */
289 	writel(0xffffffff, &mctl_com->maer);
290 
291 	return 0;
292 }
293 
mctl_sys_init(struct dram_para * para)294 static void mctl_sys_init(struct dram_para *para)
295 {
296 	struct sunxi_ccm_reg * const ccm =
297 			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
298 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
299 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
300 	struct sunxi_mctl_com_reg * const mctl_com =
301 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
302 
303 	clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
304 			CCM_DRAMPLL_CFG_SRC_PLL11);
305 
306 	clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
307 			DRAM_SIGMA_DELTA_ENABLE);
308 
309 	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
310 			CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
311 			CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
312 	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
313 
314 	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
315 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
316 	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
317 	setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
318 
319 	/* Set dram master access priority */
320 	writel(0x0, &mctl_com->mapr);
321 	writel(0x0f802f01, &mctl_ctl->sched);
322 	writel(0x0000400f, &mctl_ctl->clken);	/* normal */
323 
324 	udelay(250);
325 }
326 
sunxi_dram_init(void)327 unsigned long sunxi_dram_init(void)
328 {
329 	struct sunxi_mctl_com_reg * const mctl_com =
330 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
331 	struct sunxi_mctl_ctl_reg * const mctl_ctl =
332 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
333 
334 	struct dram_para para = {
335 		.cs1 = 0,
336 		.bank = 1,
337 		.rank = 2,
338 		.rows = 15,
339 		.bus_width = 16,
340 		.page_size = 2048,
341 	};
342 
343 	mctl_sys_init(&para);
344 
345 	if (mctl_channel_init(&para) != 0)
346 		return 0;
347 
348 	auto_detect_dram_size(&para);
349 
350 	/* Enable master software clk */
351 	writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
352 
353 	/* Set DRAM ODT MAP */
354 	if (para.rank == 2)
355 		writel(0x00000303, &mctl_ctl->odtmap);
356 	else
357 		writel(0x00000201, &mctl_ctl->odtmap);
358 
359 	return para.page_size * (para.bus_width / 8) *
360 		(1 << (para.bank + para.rank + para.rows));
361 }
362