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Searched refs:GENMASK (Results 1 – 25 of 198) sorted by relevance

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/external/u-boot/arch/mips/mach-mscc/include/mach/serval/
Dserval_icpu_cfg.h37 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
38 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
39 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
41 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
51 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
54 #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
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/external/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
Docelot_icpu_cfg.h30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
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/external/u-boot/arch/mips/mach-mscc/include/mach/jr2/
Djr2_icpu_cfg.h29 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
32 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
33 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
45 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
46 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
47 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
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/external/u-boot/arch/mips/mach-mscc/include/mach/servalt/
Dservalt_icpu_cfg.h30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
46 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
56 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
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/external/u-boot/arch/mips/mach-mscc/include/mach/luton/
Dluton_icpu_cfg.h35 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
36 #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
[all …]
/external/u-boot/drivers/mtd/nand/raw/
Ddenali.h22 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
25 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
28 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
31 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
53 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
65 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
66 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
70 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
71 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
74 #define RE_2_WE__VALUE GENMASK(5, 0)
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/external/arm-trusted-firmware/include/drivers/st/
Dstm32mp1_rcc.h237 #define RCC_OFFSET_MASK GENMASK(11, 0)
244 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
245 #define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0)
271 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
275 #define RCC_APBXDIV_MASK GENMASK(2, 0)
276 #define RCC_MPUDIV_MASK GENMASK(2, 0)
277 #define RCC_AXIDIV_MASK GENMASK(2, 0)
278 #define RCC_MCUDIV_MASK GENMASK(3, 0)
294 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
298 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
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Dstm32_uart_regs.h43 #define USART_CR1_DEDT GENMASK(20, 16)
49 #define USART_CR1_DEAT GENMASK(25, 21)
72 #define USART_CR2_STOP GENMASK(13, 12)
82 #define USART_CR2_ABRMODE GENMASK(22, 21)
86 #define USART_CR2_ADD GENMASK(31, 24)
105 #define USART_CR3_SCARCNT GENMASK(19, 17)
109 #define USART_CR3_WUS GENMASK(21, 20)
115 #define USART_CR3_RXFTCFG GENMASK(27, 25)
120 #define USART_CR3_TXFTCFG GENMASK(31, 29)
126 #define USART_BRR_DIV_FRACTION GENMASK(3, 0)
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Dstm32_i2c.h23 #define I2C_CR1_DNF GENMASK(11, 8)
38 #define I2C_CR2_SADD GENMASK(9, 0)
46 #define I2C_CR2_NBYTES GENMASK(23, 16)
53 #define I2C_OAR1_OA1 GENMASK(9, 0)
58 #define I2C_OAR2_OA2 GENMASK(7, 1)
59 #define I2C_OAR2_OA2MSK GENMASK(10, 8)
63 #define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
67 #define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
71 #define I2C_TIMINGR_SCLL GENMASK(7, 0)
72 #define I2C_TIMINGR_SCLH GENMASK(15, 8)
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Dstm32mp1_ddr_regs.h258 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
264 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
267 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
277 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
287 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(19, 12)
294 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
297 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30)
307 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
308 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
358 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
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/external/u-boot/drivers/phy/
Dmeson-gxl-usb3.c24 #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
28 #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
29 #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
32 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
33 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
39 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
40 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
41 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
45 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
46 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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Dmeson-gxl-usb2.c42 #define U2P_R0_FSEL_MASK GENMASK(19, 17)
43 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
45 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
61 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
62 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
63 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
64 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
65 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
66 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
67 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
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Dmt76x8-usb-phy.c19 #define USBPLL_FBDIV_M GENMASK(22, 16)
21 #define BG_TRIM_M GENMASK(11, 8)
23 #define BG_RBSEL_M GENMASK(7, 6)
25 #define BG_RASEL_M GENMASK(5, 4)
27 #define BGR_DIV_M GENMASK(3, 2)
32 #define VRT_VREF_SEL_M GENMASK(30, 28)
34 #define TERM_VREF_SEL_M GENMASK(26, 24)
44 #define HSTX_SRCTRL_M GENMASK(18, 16)
48 #define HSTX_DBIST_M GENMASK(31, 28)
50 #define HSRX_BIAS_EN_SEL_M GENMASK(21, 20)
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/external/u-boot/drivers/power/domain/
Dmeson-ee-pwrc.c90 { __reg, GENMASK(1, 0) }, \
91 { __reg, GENMASK(3, 2) }, \
92 { __reg, GENMASK(5, 4) }, \
93 { __reg, GENMASK(7, 6) }, \
94 { __reg, GENMASK(9, 8) }, \
95 { __reg, GENMASK(11, 10) }, \
96 { __reg, GENMASK(13, 12) }, \
97 { __reg, GENMASK(15, 14) }, \
98 { __reg, GENMASK(17, 16) }, \
99 { __reg, GENMASK(19, 18) }, \
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Dmtk-power-domain.c94 .sram_pdn_bits = GENMASK(11, 8),
100 .sram_pdn_bits = GENMASK(11, 8),
101 .sram_pdn_ack_bits = GENMASK(12, 12),
106 .sram_pdn_bits = GENMASK(11, 8),
107 .sram_pdn_ack_bits = GENMASK(12, 12),
112 .sram_pdn_bits = GENMASK(11, 8),
113 .sram_pdn_ack_bits = GENMASK(13, 12),
118 .sram_pdn_bits = GENMASK(11, 8),
123 .sram_pdn_bits = GENMASK(11, 8),
124 .sram_pdn_ack_bits = GENMASK(15, 12),
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/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3368.h59 PLL_NR_MASK = GENMASK(13, 8),
61 PLL_OD_MASK = GENMASK(3, 0),
66 PLL_NF_MASK = GENMASK(12, 0),
70 PLL_BWADJ_MASK = GENMASK(11, 0),
74 PLL_MODE_MASK = GENMASK(9, 8),
80 PLL_RESET_MASK = GENMASK(5, 5),
84 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
90 MCU_CLK_DIV_MASK = GENMASK(4, 0),
94 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
99 GMAC_DIV_CON_MASK = GENMASK(4, 0),
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/external/u-boot/drivers/pci_endpoint/
Dpcie-cadence.h25 #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
29 #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
36 #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
43 #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
45 #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
54 (GENMASK(4, 0) << ((b) * 8))
58 (GENMASK(7, 5) << ((b) * 8))
67 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
70 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
73 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
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/external/u-boot/drivers/usb/cdns3/
Dgadget.h227 #define USB_STS_USBSPEED_MASK GENMASK(6, 4)
310 #define USB_STS_LPMST_MASK GENMASK(19, 18)
347 #define USB_STS_LST_MASK GENMASK(29, 26)
385 #define USB_CMD_FADDR_MASK GENMASK(7, 1)
392 #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
402 #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
408 #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
417 #define USB_ITPN_MASK GENMASK(13, 0)
422 #define USB_LPM_HIRD_MASK GENMASK(3, 0)
529 #define EP_SEL_EPNO_MASK GENMASK(3, 0)
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/external/u-boot/drivers/adc/
Dmeson-saradc.c22 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
29 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
30 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
33 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
36 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
43 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
45 (GENMASK(2, 0) << ((_chan) * 3))
51 (GENMASK(17, 16) << ((_chan) * 2))
55 (GENMASK(1, 0) << ((_chan) * 2))
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/external/u-boot/arch/arm/mach-rockchip/rk3368/
Drk3368.c23 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
24 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
27 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
28 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
31 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
32 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
126 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); in sgrf_init()
128 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); in sgrf_init()
181 GPIO2D1_MASK = GENMASK(3, 2), in board_debug_uart_init()
185 GPIO2D0_MASK = GENMASK(1, 0), in board_debug_uart_init()
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/external/u-boot/include/linux/soc/ti/
Dcppi5.h47 #define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
59 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
61 #define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
64 #define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
66 #define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
68 #define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
70 #define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
73 #define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
90 #define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
93 #define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
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/external/u-boot/drivers/video/stm32/
Dstm32_ltdc.c70 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
71 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
73 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
74 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
76 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
77 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
79 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
80 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
89 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
90 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
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/external/u-boot/arch/arm/include/asm/arch-meson/
Dsd_emmc.h33 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
37 #define CFG_BL_LEN_MASK GENMASK(7, 4)
40 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
42 #define CFG_RC_CC_MASK GENMASK(15, 12)
48 #define STATUS_MASK GENMASK(15, 0)
49 #define STATUS_ERR_MASK GENMASK(12, 0)
50 #define STATUS_RXD_ERR_MASK GENMASK(7, 0)
61 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
/external/u-boot/arch/arm/include/asm/arch-imx8m/
Dclock_imx8mm.h26 #define MDIV_MASK GENMASK(21, 12)
28 #define PDIV_MASK GENMASK(9, 4)
30 #define SDIV_MASK GENMASK(2, 0)
32 #define KDIV_MASK GENMASK(15, 0)
433 #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
434 #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
436 #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
437 #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
439 #define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
440 #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
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/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr_regs.h239 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
245 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
248 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
258 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
268 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
281 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
282 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
312 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
316 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
329 #define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
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