1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 * Copyright (c) 2016 Andreas Färber
5 */
6
7 #include <common.h>
8 #include <syscon.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/io.h>
11 #include <asm/arch-rockchip/bootrom.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/cru_rk3368.h>
14 #include <asm/arch-rockchip/grf_rk3368.h>
15 #include <asm/arch-rockchip/hardware.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define IMEM_BASE 0xFF8C0000
20
21 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
22 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
23 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
24 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
25 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
26 #define MCU_EXSRAM_BASE (0)
27 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
28 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
29 /* experi no used, reserved value = 0 */
30 #define MCU_EXPERI_BASE (0)
31 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
32 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
33
34 static struct mm_region rk3368_mem_map[] = {
35 {
36 .virt = 0x0UL,
37 .phys = 0x0UL,
38 .size = 0x80000000UL,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 PTE_BLOCK_INNER_SHARE
41 }, {
42 .virt = 0xf0000000UL,
43 .phys = 0xf0000000UL,
44 .size = 0x10000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 /* List terminator */
50 0,
51 }
52 };
53
54 struct mm_region *mem_map = rk3368_mem_map;
55
56 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
57 [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
58 [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
59 };
60
61 #ifdef CONFIG_ARCH_EARLY_INIT_R
mcu_init(void)62 static int mcu_init(void)
63 {
64 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
65 struct rk3368_cru *cru = rockchip_get_cru();
66
67 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
68 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
69 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
70 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
71 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
72 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
73 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
74 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
75 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
76 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
77 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
78 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
79
80 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
81 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
82 (5 << MCU_CLK_DIV_SHIFT));
83
84 /* mcu dereset, for start running */
85 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
86
87 return 0;
88 }
89
arch_early_init_r(void)90 int arch_early_init_r(void)
91 {
92 return mcu_init();
93 }
94 #endif
95
96 #ifdef CONFIG_SPL_BUILD
97 /*
98 * The SPL (and also the full U-Boot stage on the RK3368) will run in
99 * secure mode (i.e. EL3) and an ATF will eventually be booted before
100 * starting up the operating system... so we can initialize the SGRF
101 * here and rely on the ATF installing the final (secure) policy
102 * later.
103 */
sgrf_soc_con_addr(unsigned int no)104 static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
105 {
106 const uintptr_t SGRF_BASE =
107 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
108
109 return SGRF_BASE + sizeof(u32) * no;
110 }
111
sgrf_busdmac_addr(unsigned int no)112 static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
113 {
114 const uintptr_t SGRF_BASE =
115 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
116 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
117 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
118
119 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
120 }
121
sgrf_init(void)122 static void sgrf_init(void)
123 {
124 struct rk3368_cru * const cru =
125 (struct rk3368_cru * const)rockchip_get_cru();
126 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
127 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
128 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
129
130 /* Set all configurable IP to 'non secure'-mode */
131 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
132 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
133 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
134
135 /*
136 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
137 * Original comment: "ddr space set no secure mode"
138 */
139 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
140 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
141 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
142
143 /* Set 'secure dma' to 'non secure'-mode */
144 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
145 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
146
147 dsb(); /* barrier */
148
149 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
150 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
151
152 dsb(); /* barrier */
153 udelay(10);
154
155 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
156 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
157 }
158
arch_cpu_init(void)159 int arch_cpu_init(void)
160 {
161 /* Reset security, so we can use DMA in the MMC drivers */
162 sgrf_init();
163
164 return 0;
165 }
166 #endif
167
168 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)169 void board_debug_uart_init(void)
170 {
171 /*
172 * N.B.: This is called before the device-model has been
173 * initialised. For this reason, we can not access
174 * the GRF address range using the syscon API.
175 */
176 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
177 struct rk3368_grf * const grf =
178 (struct rk3368_grf * const)0xff770000;
179
180 enum {
181 GPIO2D1_MASK = GENMASK(3, 2),
182 GPIO2D1_GPIO = 0,
183 GPIO2D1_UART0_SOUT = (1 << 2),
184
185 GPIO2D0_MASK = GENMASK(1, 0),
186 GPIO2D0_GPIO = 0,
187 GPIO2D0_UART0_SIN = (1 << 0),
188 };
189
190 /* Enable early UART0 on the RK3368 */
191 rk_clrsetreg(&grf->gpio2d_iomux,
192 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
193 rk_clrsetreg(&grf->gpio2d_iomux,
194 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
195 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
196 struct rk3368_pmu_grf * const pmugrf __maybe_unused =
197 (struct rk3368_pmu_grf * const)0xff738000;
198
199 enum {
200 /* UART4 */
201 GPIO0D2_MASK = GENMASK(5, 4),
202 GPIO0D2_GPIO = 0,
203 GPIO0D2_UART4_SOUT = (3 << 4),
204
205 GPIO0D3_MASK = GENMASK(7, 6),
206 GPIO0D3_GPIO = 0,
207 GPIO0D3_UART4_SIN = (3 << 6),
208 };
209
210 /* Enable early UART4 on the PX5 */
211 rk_clrsetreg(&pmugrf->gpio0d_iomux,
212 GPIO0D2_MASK | GPIO0D3_MASK,
213 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
214 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
215 struct rk3368_grf * const grf =
216 (struct rk3368_grf * const)0xff770000;
217
218 enum {
219 GPIO2A6_SHIFT = 12,
220 GPIO2A6_MASK = GENMASK(13, 12),
221 GPIO2A6_GPIO = 0,
222 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
223
224 GPIO2A5_SHIFT = 10,
225 GPIO2A5_MASK = GENMASK(11, 10),
226 GPIO2A5_GPIO = 0,
227 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
228 };
229
230 /* Enable early UART2 on the RK3368 */
231 rk_clrsetreg(&grf->gpio2a_iomux,
232 GPIO2A6_MASK, GPIO2A6_UART2_SIN);
233 rk_clrsetreg(&grf->gpio2a_iomux,
234 GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
235 #endif
236 }
237 #endif
238