/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonFrameLowering.cpp | 284 const HexagonRegisterInfo &HRI) { in needsStackFrame() argument 312 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) in needsStackFrame() 405 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in findShrunkPrologEpilog() local 437 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P) in findShrunkPrologEpilog() 438 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S) in findShrunkPrologEpilog() 442 if (needsStackFrame(I, CSR, HRI)) in findShrunkPrologEpilog() 506 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in emitPrologue() local 516 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs); in emitPrologue() 521 insertCSRRestoresInBlock(*EpilogB, CSI, HRI); in emitPrologue() 526 insertCSRRestoresInBlock(B, CSI, HRI); in emitPrologue() [all …]
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D | HexagonInstrInfo.cpp | 127 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst() argument 128 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst() 129 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst() 739 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in reduceLoopCount() local 743 (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI); in reduceLoopCount() 782 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg() local 843 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg() 844 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() 870 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; in copyPhysReg() 1016 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo() local [all …]
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D | HexagonVLIWPacketizer.cpp | 114 const HexagonRegisterInfo *HRI; member in __anonb13e59220111::HexagonPacketizer 135 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in INITIALIZE_PASS_DEPENDENCY() 207 HRI = HST.getRegisterInfo(); in runOnMachineFunction() 296 if (DepReg == HRI->getRARegister()) in isCallDependent() 300 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister()) in isCallDependent() 481 if (HII->isValidOffset(Opc, NewOff, HRI)) { in useCallersSP() 532 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) in updateOffset() 655 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToNewValueStore() 705 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore() 717 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore() [all …]
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D | HexagonVExtract.cpp | 104 const auto &HRI = *HST->getRegisterInfo(); in runOnMachineFunction() local 126 int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC), in runOnMachineFunction() 127 HRI.getSpillAlignment(VecRC)); in runOnMachineFunction() 139 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
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D | HexagonGenMux.cpp | 90 const HexagonRegisterInfo *HRI = nullptr; member in __anon8d3a7ec20111::HexagonGenMux 148 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I) in getSubRegs() 184 unsigned NR = HRI->getNumRegs(); in buildMaps() 350 LivePhysRegs LPR(*HRI); in genMuxInBlock() 353 for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S) in genMuxInBlock() 382 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction()
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D | HexagonBitSimplify.cpp | 441 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence() local 443 unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo); in parseRegSequence() 444 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence() 905 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass() local 908 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass() 909 (void)HRI; in getFinalVRegClass() 910 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass() 911 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass() 1057 : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {} in RedundantInstrElimination() 1072 const HexagonRegisterInfo &HRI; member in __anon0ea2589a0511::RedundantInstrElimination [all …]
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D | HexagonISelDAGToDAG.h | 34 const HexagonRegisterInfo *HRI; variable 39 HRI(nullptr) {} in HexagonDAGToDAGISel() 45 HRI = HST->getRegisterInfo(); in runOnMachineFunction()
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D | HexagonConstExtenders.cpp | 382 const HexagonRegisterInfo *HRI = nullptr; member 444 : Rs(R), HRI(I) {} in PrintRegister() 446 const HexagonRegisterInfo &HRI; member 452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<() 460 : Ex(E), HRI(I) {} in PrintExpr() 462 const HexagonRegisterInfo &HRI; member 469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); in operator <<() 478 : ExtI(EI), HRI(I) {} in PrintInit() 480 const HexagonRegisterInfo &HRI; member 486 << PrintExpr(P.ExtI.second, P.HRI) << ']'; in operator <<() [all …]
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D | HexagonGenInsert.cpp | 565 const HexagonRegisterInfo *HRI = nullptr; member in __anon5087ef7d0511::HexagonGenInsert 585 dbgs() << " " << printReg(I->first, HRI) << ":\n"; in dump_map() 588 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " in dump_map() 589 << PrintRegSet(LL[i].second, HRI) << '\n'; in dump_map() 798 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms() 799 << " AVs: " << PrintORL(AVs, HRI) << "\n"; in findRecordInsertForms() 863 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms() 868 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" in findRecordInsertForms() 915 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms() 916 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms() [all …]
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D | HexagonBranchRelaxation.cpp | 70 const HexagonRegisterInfo *HRI; member 97 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
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D | HexagonFrameLowering.h | 116 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const; 118 const HexagonRegisterInfo &HRI) const;
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D | HexagonRDFOpt.cpp | 295 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() local 303 DataFlowGraph G(MF, HII, HRI, *MDT, MDF, TOI); in runOnMachineFunction()
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D | HexagonVLIWPacketizer.h | 68 const HexagonRegisterInfo *HRI; variable
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D | HexagonOptAddrMode.cpp | 84 const HexagonRegisterInfo *HRI = nullptr; member in __anondc8295810111::HexagonOptAddrMode 345 return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); in isValidOffset() 781 HRI = HST.getRegisterInfo(); in runOnMachineFunction() 786 DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI); in runOnMachineFunction()
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D | HexagonISelLowering.cpp | 371 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall() local 373 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT); in LowerCall() 437 unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in LowerCall() 508 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv); in LowerCall() 576 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM() local 577 unsigned LR = HRI.getRARegister(); in LowerINLINEASM() 959 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR() local 979 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR() 985 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR() local 993 HRI.getFrameRegister(), VT); in LowerFRAMEADDR() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonFrameLowering.cpp | 242 const HexagonRegisterInfo &HRI) { in needsStackFrame() argument 271 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) in needsStackFrame() 346 auto &HRI = *HST.getRegisterInfo(); in findShrunkPrologEpilog() local 377 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P) in findShrunkPrologEpilog() 378 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S) in findShrunkPrologEpilog() 382 if (needsStackFrame(I, CSR, HRI)) in findShrunkPrologEpilog() 444 auto &HRI = *HST.getRegisterInfo(); in emitPrologue() local 454 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs); in emitPrologue() 458 insertCSRRestoresInBlock(*EpilogB, CSI, HRI); in emitPrologue() 463 insertCSRRestoresInBlock(B, CSI, HRI); in emitPrologue() [all …]
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D | HexagonVLIWPacketizer.cpp | 89 const HexagonRegisterInfo *HRI; member in __anon15f0d18a0111::HexagonPacketizer 110 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in INITIALIZE_PASS_DEPENDENCY() 178 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() 271 if (DepReg == HRI->getRARegister()) in isCallDependent() 275 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister()) in isCallDependent() 279 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg); in isCallDependent() 544 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToNewValueStore() 594 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore() 606 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore() 652 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore() [all …]
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D | HexagonInstrInfo.cpp | 114 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst() argument 115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) && in isDblRegForSubInst() 116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg)); in isDblRegForSubInst() 764 auto &HRI = getRegisterInfo(); in copyPhysReg() local 826 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag) in copyPhysReg() 827 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg() 847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg); in copyPhysReg() 849 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag); in copyPhysReg() 850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg); in copyPhysReg() 852 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg() [all …]
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D | HexagonGenMux.cpp | 42 HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) { in HexagonGenMux() 59 const HexagonRegisterInfo *HRI; member in __anon4bcf0f2a0111::HexagonGenMux 109 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I) in getSubRegs() 148 unsigned NR = HRI->getNumRegs(); in buildMaps() 315 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction()
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D | HexagonGenInsert.cpp | 467 HexagonGenInsert() : MachineFunctionPass(ID), HII(0), HRI(0) { in HexagonGenInsert() 523 const HexagonRegisterInfo *HRI; member in __anonc5cb86e50911::HexagonGenInsert 542 dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; in dump_map() 545 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " in dump_map() 546 << PrintRegSet(LL[i].second, HRI) << '\n'; in dump_map() 760 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI) in findRecordInsertForms() 761 << " AVs: " << PrintORL(AVs, HRI) << "\n"; in findRecordInsertForms() 824 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; in findRecordInsertForms() 829 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" in findRecordInsertForms() 877 dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) in findRecordInsertForms() [all …]
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D | HexagonBranchRelaxation.cpp | 58 const HexagonRegisterInfo *HRI; member 85 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
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D | HexagonRDFOpt.cpp | 282 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() local 289 HexagonRegisterAliasInfo HAI(HRI); in runOnMachineFunction() 291 DataFlowGraph G(MF, HII, HRI, *MDT, MDF, HAI, TOI); in runOnMachineFunction()
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D | HexagonFrameLowering.h | 91 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const; 93 const HexagonRegisterInfo &HRI) const;
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D | HexagonVLIWPacketizer.h | 41 const HexagonRegisterInfo *HRI; variable
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D | HexagonBitSimplify.cpp | 2184 auto &HRI = *HST.getRegisterInfo(); in runOnMachineFunction() local 2193 const HexagonEvaluator HE(HRI, MRI, HII, MF); in runOnMachineFunction() 2213 CopyPropagation CopyP(HRI, MRI); in runOnMachineFunction() 2307 HII(0), HRI(0), MRI(0), BTP(0) { in HexagonLoopRescheduling() 2315 const HexagonRegisterInfo *HRI; member in __anone3296a020911::HexagonLoopRescheduling 2553 dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" in processLoop() 2554 << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() in processLoop() 2555 << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" in processLoop() 2675 << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub) in processLoop() 2676 << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; in processLoop() [all …]
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