Searched refs:ID_AA64PFR0_EL2_SHIFT (Results 1 – 12 of 12) sorted by relevance
47 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in socfpga_get_spsr_for_bl33_entry()
115 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in marvell_get_spsr_for_bl33_entry()
65 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in poplar_get_spsr_for_bl33_entry()
68 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
140 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
142 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
48 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in k3_get_spsr_for_bl33_entry()
55 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in sq_get_spsr_for_bl33_entry()
96 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
59 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
64 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; in get_spsr_for_bl33_entry()
133 #define ID_AA64PFR0_EL2_SHIFT U(8) macro