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1 /*
2  * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <stdbool.h>
9 
10 #include <platform_def.h>
11 
12 #include <arch_helpers.h>
13 #include <context.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <drivers/arm/cci.h>
17 #include <drivers/console.h>
18 #include <lib/el3_runtime/context_mgmt.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables.h>
21 #include <plat/common/platform.h>
22 
23 #include <imx8qm_pads.h>
24 #include <imx8_iomux.h>
25 #include <imx8_lpuart.h>
26 #include <plat_imx8.h>
27 #include <sci/sci.h>
28 #include <sec_rsrc.h>
29 
30 static const unsigned long BL31_COHERENT_RAM_START	= BL_COHERENT_RAM_BASE;
31 static const unsigned long BL31_COHERENT_RAM_END	= BL_COHERENT_RAM_END;
32 static const unsigned long BL31_RO_START		= BL_CODE_BASE;
33 static const unsigned long BL31_RO_END			= BL_CODE_END;
34 static const unsigned long BL31_RW_END			= BL_END;
35 
36 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
37 
38 static entry_point_info_t bl32_image_ep_info;
39 static entry_point_info_t bl33_image_ep_info;
40 
41 #define UART_PAD_CTRL	(PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
42 			(SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
43 			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
44 			(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
45 			(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
46 
47 const static int imx8qm_cci_map[] = {
48 	CLUSTER0_CCI_SLVAE_IFACE,
49 	CLUSTER1_CCI_SLVAE_IFACE
50 };
51 
52 static const mmap_region_t imx_mmap[] = {
53 	MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW),
54 	{0}
55 };
56 
get_spsr_for_bl33_entry(void)57 static uint32_t get_spsr_for_bl33_entry(void)
58 {
59 	unsigned long el_status;
60 	unsigned long mode;
61 	uint32_t spsr;
62 
63 	/* figure out what mode we enter the non-secure world */
64 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
65 	el_status &= ID_AA64PFR0_ELX_MASK;
66 
67 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
68 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
69 
70 	return spsr;
71 }
72 
73 #if DEBUG_CONSOLE_A53
lpuart32_serial_setbrg(unsigned int base,int baudrate)74 static void lpuart32_serial_setbrg(unsigned int base, int baudrate)
75 {
76 	unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr;
77 	unsigned int diff1, diff2, tmp, rate;
78 
79 	if (baudrate == 0)
80 		panic();
81 
82 	sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
83 
84 	baud_diff = baudrate;
85 	osr = 0;
86 	sbr = 0;
87 	for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
88 		tmp_sbr = (rate / (baudrate * tmp_osr));
89 		if (tmp_sbr == 0)
90 			tmp_sbr = 1;
91 
92 		/* calculate difference in actual baud w/ current values */
93 		diff1 = rate / (tmp_osr * tmp_sbr) - baudrate;
94 		diff2 = rate / (tmp_osr * (tmp_sbr + 1));
95 
96 		/* select best values between sbr and sbr+1 */
97 		if (diff1 > (baudrate - diff2)) {
98 			diff1 = baudrate - diff2;
99 			tmp_sbr++;
100 		}
101 
102 		if (diff1 <= baud_diff) {
103 			baud_diff = diff1;
104 			osr = tmp_osr;
105 			sbr = tmp_sbr;
106 		}
107 	}
108 
109 	tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD);
110 
111 	if ((osr > 3) && (osr < 8))
112 		tmp |= LPUART_BAUD_BOTHEDGE_MASK;
113 
114 	tmp &= ~LPUART_BAUD_OSR_MASK;
115 	tmp |= LPUART_BAUD_OSR(osr - 1);
116 	tmp &= ~LPUART_BAUD_SBR_MASK;
117 	tmp |= LPUART_BAUD_SBR(sbr);
118 
119 	/* explicitly disable 10 bit mode & set 1 stop bit */
120 	tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
121 
122 	mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp);
123 }
124 
lpuart32_serial_init(unsigned int base)125 static int lpuart32_serial_init(unsigned int base)
126 {
127 	unsigned int tmp;
128 
129 	/* disable TX & RX before enabling clocks */
130 	tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
131 	tmp &= ~(CTRL_TE | CTRL_RE);
132 	mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
133 
134 	mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0);
135 	mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE));
136 
137 	mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0);
138 
139 	/* provide data bits, parity, stop bit, etc */
140 	lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE);
141 
142 	/* eight data bits no parity bit */
143 	tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
144 	tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
145 	mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
146 
147 	mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE);
148 
149 	mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
150 	mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
151 	mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A);
152 
153 	return 0;
154 }
155 #endif
156 
mx8_partition_resources(void)157 void mx8_partition_resources(void)
158 {
159 	sc_rm_pt_t secure_part, os_part;
160 	sc_rm_mr_t mr, mr_record = 64;
161 	sc_faddr_t start, end;
162 	bool owned, owned2;
163 	sc_err_t err;
164 	int i;
165 
166 	err = sc_rm_get_partition(ipc_handle, &secure_part);
167 
168 	err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,
169 		false, false, false);
170 
171 	err = sc_rm_set_parent(ipc_handle, os_part, secure_part);
172 
173 	/* set secure resources to NOT-movable */
174 	for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) {
175 		err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i],
176 			secure_rsrcs[i], false);
177 		if (err)
178 			ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
179 				secure_rsrcs[i], err);
180 	}
181 
182 	owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0);
183 	if (owned) {
184 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
185 				SC_R_M4_0_PID0, false);
186 		if (err)
187 			ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
188 				SC_R_M4_0_PID0, err);
189 	}
190 
191 	owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0);
192 	if (owned2) {
193 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
194 				SC_R_M4_1_PID0, false);
195 		if (err)
196 			ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
197 				SC_R_M4_1_PID0, err);
198 	}
199 	/* move all movable resources and pins to non-secure partition */
200 	err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);
201 	if (err)
202 		ERROR("sc_rm_move_all: %u\n", err);
203 
204 	/* iterate through peripherals to give NS OS part access */
205 	for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) {
206 		err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i],
207 			os_part, SC_RM_PERM_FULL);
208 		if (err)
209 			ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \
210 				ret %u\n", ns_access_allowed[i], err);
211 	}
212 
213 	if (owned) {
214 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
215 				SC_R_M4_0_PID0, true);
216 		if (err)
217 			ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
218 				SC_R_M4_0_PID0, err);
219 		err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0);
220 		if (err)
221 			ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
222 				SC_R_M4_0_PID0, err);
223 	}
224 	if (owned2) {
225 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
226 				SC_R_M4_1_PID0, true);
227 		if (err)
228 			ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
229 				SC_R_M4_1_PID0, err);
230 		err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0);
231 		if (err)
232 			ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
233 				SC_R_M4_1_PID0, err);
234 	}
235 
236 	/*
237 	 * sc_rm_set_peripheral_permissions
238 	 * sc_rm_set_memreg_permissions
239 	 * sc_rm_set_pin_movable
240 	 */
241 
242 	for (mr = 0; mr < 64; mr++) {
243 		owned = sc_rm_is_memreg_owned(ipc_handle, mr);
244 		if (owned) {
245 			err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
246 			if (err)
247 				ERROR("Memreg get info failed, %u\n", mr);
248 			NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
249 			if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
250 				mr_record = mr; /* Record the mr for ATF running */
251 			} else {
252 				err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
253 				if (err)
254 					ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
255 						err %d\n", start, end, err);
256 			}
257 		}
258 	}
259 
260 	if (mr_record != 64) {
261 		err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);
262 		if (err)
263 			ERROR("Memreg get info failed, %u\n", mr_record);
264 		if ((BL31_LIMIT - 1) < end) {
265 			err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
266 			if (err)
267 				ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
268 					(sc_faddr_t)BL31_LIMIT, end);
269 			err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
270 			if (err)
271 				ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
272 					(sc_faddr_t)BL31_LIMIT, end);
273 		}
274 
275 		if (start < (BL31_BASE - 1)) {
276 			err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
277 			if (err)
278 				ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
279 					start, (sc_faddr_t)BL31_BASE - 1);
280 			err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
281 				if (err)
282 					ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
283 						start, (sc_faddr_t)BL31_BASE - 1);
284 		}
285 	}
286 
287 	if (err)
288 		NOTICE("Partitioning Failed\n");
289 	else
290 		NOTICE("Non-secure Partitioning Succeeded\n");
291 
292 }
293 
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)294 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
295 				u_register_t arg2, u_register_t arg3)
296 {
297 #if DEBUG_CONSOLE
298 	static console_lpuart_t console;
299 #endif
300 	if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
301 		panic();
302 
303 #if DEBUG_CONSOLE_A53
304 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON);
305 	sc_pm_clock_rate_t rate = 80000000;
306 	sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
307 	sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false);
308 
309 	/* configure UART pads */
310 	sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL);
311 	sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL);
312 	sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL);
313 	sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL);
314 	lpuart32_serial_init(IMX_BOOT_UART_BASE);
315 #endif
316 
317 #if DEBUG_CONSOLE
318 	console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
319 		     IMX_CONSOLE_BAUDRATE, &console);
320 #endif
321 
322 	/* turn on MU1 for non-secure OS/Hypervisor */
323 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
324 	/* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
325 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
326 	sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
327 	mmio_write_32(IMX_GPT_LPCG_BASE, mmio_read_32(IMX_GPT_LPCG_BASE) | (1 << 25));
328 
329 	/*
330 	 * create new partition for non-secure OS/Hypervisor
331 	 * uses global structs defined in sec_rsrc.h
332 	 */
333 	mx8_partition_resources();
334 
335 	bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
336 	bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
337 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
338 
339 	/* init the first cluster's cci slave interface */
340 	cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT);
341 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
342 }
343 
bl31_plat_arch_setup(void)344 void bl31_plat_arch_setup(void)
345 {
346 	unsigned long ro_start = BL31_RO_START;
347 	unsigned long ro_size = BL31_RO_END - BL31_RO_START;
348 	unsigned long rw_start = BL31_RW_START;
349 	unsigned long rw_size = BL31_RW_END - BL31_RW_START;
350 #if USE_COHERENT_MEM
351 	unsigned long coh_start = BL31_COHERENT_RAM_START;
352 	unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START;
353 #endif
354 
355 	mmap_add_region(ro_start, ro_start, ro_size,
356 		MT_RO | MT_MEMORY | MT_SECURE);
357 	mmap_add_region(rw_start, rw_start, rw_size,
358 		MT_RW | MT_MEMORY | MT_SECURE);
359 	mmap_add(imx_mmap);
360 
361 #if USE_COHERENT_MEM
362 	mmap_add_region(coh_start, coh_start, coh_size,
363 			MT_DEVICE | MT_RW | MT_SECURE);
364 #endif
365 
366 	/* setup xlat table */
367 	init_xlat_tables();
368 	/* enable the MMU */
369 	enable_mmu_el3(0);
370 }
371 
bl31_platform_setup(void)372 void bl31_platform_setup(void)
373 {
374 	plat_gic_driver_init();
375 	plat_gic_init();
376 }
377 
bl31_plat_get_next_image_ep_info(unsigned int type)378 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
379 {
380 	if (type == NON_SECURE)
381 		return &bl33_image_ep_info;
382 	if (type == SECURE)
383 		return &bl32_image_ep_info;
384 
385 	return NULL;
386 }
387 
plat_get_syscnt_freq2(void)388 unsigned int plat_get_syscnt_freq2(void)
389 {
390 	return COUNTER_FREQUENCY;
391 }
392 
bl31_plat_runtime_setup(void)393 void bl31_plat_runtime_setup(void)
394 {
395 	return;
396 }
397