Searched refs:INREG (Results 1 – 18 of 18) sorted by relevance
70 dword = INREG(reg); \76 dword = INREG(disp_reg_base + reg); \82 dword = INREG(aud_reg_base + reg); \86 #define read_aud_reg(reg) INREG(aud_reg_base + (reg))535 dword = INREG(AUD_VID_DID); in dump_eaglelake()539 dword = INREG(AUD_RID); in dump_eaglelake()545 dword = INREG(SDVOB); in dump_eaglelake()552 dword = INREG(SDVOC); in dump_eaglelake()559 dword = INREG(PORT_HOTPLUG_EN); in dump_eaglelake()569 dword = INREG(VIDEO_DIP_CTL); in dump_eaglelake()[all …]
45 current = INREG(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in main()46 max = INREG(BLC_PWM_PCH_CTL2) >> 16; in main()55 (INREG(BLC_PWM_CPU_CTL) &~ BACKLIGHT_DUTY_CYCLE_MASK) | v); in main()56 (void) INREG(BLC_PWM_CPU_CTL); in main()
340 ctl_val = INREG(ctl_reg); in load_infoframe()345 ctl_val = INREG(ctl_reg); in load_infoframe()351 ctl_val = INREG(ctl_reg); in load_infoframe()353 frame->data32[i] = INREG(data_reg); in load_infoframe()388 uint32_t val = INREG(port); in dump_port_info()441 val = INREG(reg); in dump_avi_info()540 val = INREG(reg); in dump_vendor_info()575 val = INREG(reg); in dump_gamut_info()603 val = INREG(reg); in dump_spd_info()638 uint32_t val = INREG(reg); in dump_transcoder_info()[all …]
87 conf = INREG(PIPECONF[intel_pipe]); in read_pipe_info()88 htotal = INREG(HTOTAL[intel_pipe]); in read_pipe_info()89 vtotal = INREG(VTOTAL[intel_pipe]); in read_pipe_info()90 src = INREG(PIPESRC[intel_pipe]); in read_pipe_info()91 ctrl1 = INREG(PF_CTRL1[intel_pipe]); in read_pipe_info()92 win_sz = INREG(PF_WIN_SZ[intel_pipe]); in read_pipe_info()
89 ring_head = INREG(LP_RING + RING_HEAD) & HEAD_ADDR; in main()90 ring_tail = INREG(LP_RING + RING_TAIL) & TAIL_ADDR; in main()
125 swf14 = INREG(SWF14); in main()
38 uint32_t val = INREG(reg); in read_and_print_reg()
365 val = INREG(reg->mmio_offset + reg->addr); in read_register()
504 char is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B); in DEBUGSTRING()510 if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == in DEBUGSTRING()
79 return INREG(vlv_offset + reg); in read_reg()
41 return INREG(display_base + addr); in read_reg()
70 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro78 tmp = INREG(addr); in _OUTREGP()98 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()110 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()125 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()252 data = INREG(CLOCK_CNTL_DATA); in __INPLL()
114 u32 tom = INREG(NB_TOM); in radeon_identify_vram()124 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); in radeon_identify_vram()135 tmp = INREG(CONFIG_MEMSIZE); in radeon_identify_vram()160 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) in radeon_identify_vram()165 tmp = INREG(MEM_CNTL); in radeon_identify_vram()577 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeon_probe()
5 ; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]15 ; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
45 uint32_t INREG(uint32_t reg);
322 uint32_t INREG(uint32_t reg) in INREG() function
43 val = INREG(HSW_PWR_WELL_CTL2); in lpsp_is_enabled()