| /external/gemmlowp/internal/ |
| D | simd_wrappers_msa.h | 91 template <int Lane>
93 return __builtin_msa_copy_s_w(value, Lane);
96 template <int Lane>
98 static_assert(Lane >= 0 && Lane <= 3, "");
99 return __builtin_msa_splati_w(value, Lane);
114 template <int Lane>
116 static_assert(Lane >= 0 && Lane <= 3, "");
117 return __builtin_msa_mulv_w(a, __builtin_msa_splati_w(b, Lane));
146 template <int Lane>
148 static_assert(Lane >= 0 && Lane <= 3, "");
[all …]
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| D | simd_wrappers_sse.h | 72 template <int Lane>
74 return _mm_extract_epi32(value, Lane);
77 template <int Lane>
79 return _mm_shuffle_epi32(value, _MM_SHUFFLE(Lane, Lane, Lane, Lane));
94 template <int Lane>
96 return Mul(a, DupLane<Lane>(b));
107 template <int Lane>
109 *acc = Add(*acc, MulByRhsLane<Lane>(lhs, rhs));
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| D | simd_wrappers_neon.h | 76 template <int Lane>
78 return vgetq_lane_s32(value, Lane);
81 template <int Lane>
83 switch (Lane) {
93 static_assert(Lane >= 0 && Lane <= 3, "");
112 template <int Lane>
114 switch (Lane) {
124 static_assert(Lane >= 0 && Lane <= 3, "");
137 template <int Lane>
139 switch (Lane) {
[all …]
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| /external/gemmlowp/meta/generators/ |
| D | zip_Nx8_neon.py | 101 emitter.EmitVLoad('1.8', emitter.Lane(lane.load, 0),
106 emitter.EmitVLoad('1.16', emitter.Lane(lane.load, 0),
111 emitter.EmitVLoad('1.16', emitter.Lane(lane.load, 0),
115 emitter.EmitVLoad('1.8', emitter.Lane(lane.load, 2),
120 emitter.EmitVLoad('1.32', emitter.Lane(lane.load, 0),
125 emitter.EmitVLoad('1.32', emitter.Lane(lane.load, 0),
129 emitter.EmitVLoad('1.8', emitter.Lane(lane.load, 4),
134 emitter.EmitVLoad('1.32', emitter.Lane(lane.load, 0),
138 emitter.EmitVLoad('1.16', emitter.Lane(lane.load, 2),
143 emitter.EmitVLoad('1.32', emitter.Lane(lane.load, 0),
[all …]
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| D | neon_emitter.py | 448 self.Lane(32, destination, 0),
451 self.Lane(16, destination, 2),
454 self.Lane(8, destination, 6),
458 self.Lane(32, destination, 0),
461 self.Lane(16, destination, 2),
465 self.Lane(32, destination, 0),
468 self.Lane(8, destination, 4),
472 self.Lane(32, destination, 0),
476 self.Lane(16, destination, 0),
479 self.Lane(8, destination, 2),
[all …]
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| D | qnt_Nx8_neon.py | 144 emitter.EmitVLoad('1.32', emitter.Lane(
156 emitter.EmitVLoad('1.32', emitter.Lane(
170 emitter.EmitVLoad('1.32', emitter.Lane(
186 emitter.EmitVLoad('1.32', emitter.Lane(
201 emitter.EmitVStore('1.8', emitter.Lane(lane[0], 0),
205 emitter.EmitVStore('1.16', emitter.Lane(lane[0], 0),
209 emitter.EmitVStore('1.16', emitter.Lane(lane[0], 0),
212 emitter.EmitVStore('1.8', emitter.Lane(lane[0], 2),
216 emitter.EmitVStore('1.32', emitter.Lane(lane[0], 0),
220 emitter.EmitVStore('1.32', emitter.Lane(lane[0], 0),
[all …]
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| D | mul_Nx8_Mx8_neon.py | 191 emitter.EmitVDup('32', duplicated[0], emitter.Lane(values, 0))
193 emitter.EmitVDup('32', duplicated[0], emitter.Lane(values, 0))
194 emitter.EmitVDup('32', duplicated[1], emitter.Lane(values, 1))
196 emitter.EmitVDup('32', duplicated[0], emitter.Lane(
198 emitter.EmitVDup('32', duplicated[1], emitter.Lane(
200 emitter.EmitVDup('32', duplicated[2], emitter.Lane(
203 emitter.EmitVDup('32', duplicated[0], emitter.Lane(
205 emitter.EmitVDup('32', duplicated[1], emitter.Lane(
207 emitter.EmitVDup('32', duplicated[2], emitter.Lane(
209 emitter.EmitVDup('32', duplicated[3], emitter.Lane(
[all …]
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| D | neon_emitter_64.py | 885 self.Lane(32, destinations[0], leftover_loaded / 32),
891 self.Lane(16, destinations[0], leftover_loaded / 16),
897 self.Lane(8, destinations[0], leftover_loaded / 8),
1001 self.Lane(32, sources[0], leftover_stored / 32),
1007 self.Lane(16, sources[0], leftover_stored / 16),
1013 self.Lane(8, sources[0], leftover_stored / 8),
1037 self.Lane(32, source, 0),
1048 self.Lane(32, source, 2),
1144 self.Lane(8, block[0], i), input_deref, stride)
1151 self.Lane(16, block[i / 4], i % 4), input_deref,
[all …]
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| /external/u-boot/arch/arm/dts/ |
| D | armada-8040-mcbin.dts | 166 * Lane 0: PCIe0 (x4)
167 * Lane 1: PCIe0 (x4)
168 * Lane 2: PCIe0 (x4)
169 * Lane 3: PCIe0 (x4)
170 * Lane 4: SFI (10G)
171 * Lane 5: SATA1
281 * Lane 0: SGMII1
282 * Lane 1: SATA 0
283 * Lane 2: USB HOST 0
284 * Lane 3: SATA1
[all …]
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| D | armada-8040-clearfog-gt-8k.dts | 155 * Lane 0: PCIe0 (x1)
156 * Lane 1: Not connected
157 * Lane 2: SFI (10G)
158 * Lane 3: Not connected
159 * Lane 4: USB 3.0 host port1 (can be PCIe)
160 * Lane 5: Not connected
267 * Lane 0: SATA 1 (RX swapped). Can be PCIe0
268 * Lane 1: Not used
269 * Lane 2: USB HOST 0
270 * Lane 3: SGMII1 - Connected to 1512 port
[all …]
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| D | armada-8040-db.dts | 121 * Lane 0: PCIe0 (x1)
122 * Lane 1: SATA0
123 * Lane 2: SFI (10G)
124 * Lane 3: SATA1
125 * Lane 4: USB3_HOST1
126 * Lane 5: PCIe2 (x1)
220 * Lane 0: PCIe0 (x1)
221 * Lane 1: SATA0
222 * Lane 2: SFI (10G)
223 * Lane 3: SATA1
[all …]
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| D | armada-xp-gp.dts | 186 /* Port 0, Lane 0 */
190 /* Port 2, Lane 0 */
194 /* Port 3, Lane 0 */
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| D | armada-xp-maxbcm.dts | 138 /* Port 0, Lane 0 */
142 /* Port 2, Lane 0 */
146 /* Port 3, Lane 0 */
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 69 const DebugLoc &DL, unsigned Reg, unsigned Lane,
75 unsigned Lane, const TargetRegisterClass *TRC);
89 unsigned Lane, unsigned ToInsert);
421 unsigned Lane, bool QPR) { in createDupLane() argument
427 .addImm(Lane) in createDupLane()
436 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
443 .addReg(DReg, 0, Lane); in createExtractSubreg()
481 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
489 .addImm(Lane); in createInsertSubreg()
546 unsigned Lane; in optimizeAllLanesPattern() local
[all …]
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| /external/u-boot/board/freescale/ls1028a/ |
| D | README | 47 - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
49 - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
51 - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
53 - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
129 - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
131 - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
133 - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
135 - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
139 - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
141 Lane 3 connects to 1x7 header to support SATA devices
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 71 const DebugLoc &DL, unsigned Reg, unsigned Lane,
77 unsigned Lane, const TargetRegisterClass *TRC);
91 unsigned Lane, unsigned ToInsert);
429 unsigned Lane, bool QPR) { in createDupLane() argument
438 .addImm(Lane)); in createDupLane()
446 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
453 .addReg(DReg, 0, Lane); in createExtractSubreg()
493 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
501 .addImm(Lane); in createInsertSubreg()
558 unsigned Lane; in optimizeAllLanesPattern() local
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 125 int Lane; member
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { } in SpilledReg()
128 bool hasLane() { return Lane != -1;} in hasLane()
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| D | SIMachineFunctionInfo.cpp | 200 unsigned Lane = (Offset / 4) % 64; in getSpilledReg() local
203 Spill.Lane = Lane; in getSpilledReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | LaneBitmask.h | 85 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
86 return LaneBitmask(Type(1) << Lane); in getLane()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Vectorize/ |
| D | VPlan.cpp | 149 !(State->Instance->Part == 0 && State->Instance->Lane == 0); in execute()
210 for (unsigned Lane = 0, VF = State->VF; Lane < VF; ++Lane) { in execute() local
211 State->Instance->Lane = Lane; in execute()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InterleavedAccess.cpp | 437 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
439 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
612 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
614 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
618 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | InterleavedAccessPass.cpp | 216 unsigned Lane = J * Factor + I; in isReInterleaveMask() local
217 unsigned NextLane = Lane + Factor; in isReInterleaveMask()
218 int LaneValue = Mask[Lane]; in isReInterleaveMask()
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| /external/u-boot/board/freescale/t208xrdb/ |
| D | README | 52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
56 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
57 - SerDes-2 Lane G-H: to SATA1 & SATA2
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 196 int Lane = -1; member
199 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {} in SpilledReg()
201 bool hasLane() { return Lane != -1;} in hasLane()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 1552 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts() local
1553 unsigned LaneIdx = Lane * VWidthPerLane; in SimplifyDemandedVectorElts()
1557 OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt); in SimplifyDemandedVectorElts()
1573 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts() local
1574 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane); in SimplifyDemandedVectorElts()
1576 LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum); in SimplifyDemandedVectorElts()
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