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Searched refs:MCTL_CR_CHANNEL (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun6i.c271 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 | in mctl_com_init()
374 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE | in sunxi_dram_init()
406 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) | in sunxi_dram_init()
Ddram_sun8i_a33.c38 MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | in mctl_set_cr()
Ddram_sun8i_a83t.c37 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a33.h168 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro
Ddram_sun8i_a83t.h190 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro
Ddram_sun6i.h260 #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) macro