| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rk3399.h | 69 #define MHz 1000000 macro
71 #define OSC_HZ (24*MHz)
72 #define LPLL_HZ (600*MHz)
73 #define BPLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_L_HZ (300*MHz)
81 #define ATCLK_CORE_L_HZ (300*MHz)
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| D | cru_rk3328.h | 47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
56 #define PCLK_DBG_HZ (300 * MHz)
62 #define PWM_CLOCK_HZ (74 * MHz)
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| D | cru_px30.h | 10 #define MHz 1000000 macro
12 #define OSC_HZ (24 * MHz)
14 #define APLL_HZ (600 * MHz)
15 #define GPLL_HZ (1200 * MHz)
16 #define NPLL_HZ (1188 * MHz)
17 #define ACLK_BUS_HZ (200 * MHz)
18 #define HCLK_BUS_HZ (150 * MHz)
19 #define PCLK_BUS_HZ (100 * MHz)
20 #define ACLK_PERI_HZ (200 * MHz)
21 #define HCLK_PERI_HZ (150 * MHz)
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| D | cru_rk322x.h | 10 #define MHz 1000000 macro
11 #define OSC_HZ (24 * MHz)
13 #define APLL_HZ (600 * MHz)
14 #define GPLL_HZ (594 * MHz)
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| D | cru_rk3128.h | 11 #define MHz 1000000 macro
12 #define OSC_HZ (24 * MHz)
14 #define APLL_HZ (600 * MHz)
15 #define GPLL_HZ (594 * MHz)
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| /external/tcpdump/tests/ |
| D | ieee802.11_exthdr.out | 1 10016360us tsft 1.0 Mb/s 2412 MHz 11b -22dBm signal -86dBm noise antenna 1 [bit 32] Probe Request (…
2 10018922us tsft 1.0 Mb/s 2412 MHz 11b -19dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment …
4 10085301us tsft 1.0 Mb/s 2412 MHz 11b -19dBm signal -86dBm noise antenna 1 [bit 32] Probe Request (…
5 10087718us tsft 1.0 Mb/s 2412 MHz 11b -18dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment …
7 10284358us tsft 1.0 Mb/s 2412 MHz 11b -61dBm signal -86dBm noise antenna 1 [bit 32] Probe Request (…
8 10288217us tsft 1.0 Mb/s 2412 MHz 11b -46dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment …
10 10351366us tsft 1.0 Mb/s 2412 MHz 11b -70dBm signal -86dBm noise antenna 1 [bit 32] Probe Request (…
11 10353769us tsft 1.0 Mb/s 2412 MHz 11b -57dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment …
13 10418368us tsft 1.0 Mb/s 2412 MHz 11b -67dBm signal -86dBm noise antenna 1 [bit 32] Probe Request (…
14 10420929us tsft 1.0 Mb/s 2412 MHz 11b -73dBm signal -86dBm noise antenna 0 [bit 32] Acknowledgment …
[all …]
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| D | ieee802.11_rx-stbc.out | 1 7268us tsft 2462 MHz 11n -51dBm signal antenna 1 150.0 Mb/s MCS 7 40 MHz short GI RX-STBC1 Data IV:…
2 119738173us tsft 2462 MHz 11n -46dBm signal antenna 1 135.0 Mb/s MCS 7 40 MHz long GI RX-STBC2 Data…
3 470382336us tsft 2462 MHz 11n -45dBm signal antenna 1 150.0 Mb/s MCS 7 40 MHz short GI RX-STBC3 Dat…
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| /external/u-boot/doc/ |
| D | README.Heterogeneous-SoCs | 90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
93 CCB:666.667 MHz,
94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
95 CPRI:600 MHz
96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
97 FMAN1: 666.667 MHz
98 QMAN: 333.333 MHz
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| D | README.fsl-hwconfig | 11 route either a 11.2896MHz or a 12.288MHz clock. The default is
12 12.288MHz. This option has two effects. First, the MUX on the board
18 Select the 11.2896MHz clock
21 Select the 12.288MHz clock
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| /external/u-boot/board/freescale/bsc9132qds/ |
| D | README | 23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
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| /external/u-boot/board/freescale/t102xqds/ |
| D | t1024_sd_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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| D | t1024_spi_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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| D | t1024_nand_rcw.cfg | 1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
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| D | README | 114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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| /external/u-boot/board/boundary/nitrogen6x/ |
| D | ddr-setup.cfg | 18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
20 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
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| /external/u-boot/board/freescale/t208xrdb/ |
| D | t2080_spi_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
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| D | t2080_nand_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
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| D | t2080_sd_rcw.cfg | 5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
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| /external/u-boot/board/freescale/p1022ds/ |
| D | README | 13 'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
17 is 11MHz), disable eTsec2 and TDM
20 and AUDIO codec clock sources only setting as 11MHz or 12MHz !
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| /external/u-boot/board/sbc8548/ |
| D | README | 5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
26 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
29 The second enables PCI support and builds for a 33MHz clock rate. Note
30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
31 will clock down to a 33MHz base clock instead of the default 66MHz. This
33 were previously running at 66MHz. If you want to use a 33MHz PCI card,
35 to flash prior to powering down the board and inserting the 33MHz PCI
40 default 66MHz. Options four and five are just repeats of option two
45 a 33MHz PCI configuration is currently untested.)
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| /external/u-boot/board/freescale/bsc9131rdb/ |
| D | README | 21 ECC, up to 400-MHz clock/800 MHz data rate
76 Core MHz/CCB MHz/DDR(MT/s)
92 1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
94 2. NAND Flash with sysclk 100MHz(J16 on RDB open)
96 3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
98 4. SPI Flash with sysclk 100MHz(J16 on RDB open)
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| /external/u-boot/doc/board/freescale/ |
| D | b4860qds.rst | 26 each runs at up to 1866.67 MHz
34 CoreNet fabric interconnect runs at 667 MHz and supports coherent and
152 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
185 66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
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| /external/u-boot/board/sbc8349/ |
| D | README | 101 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
106 The second enables PCI support and builds for a 33MHz clock rate. Note
107 that if a 33MHz 32bit card is inserted in the slot, then the whole board
108 will clock down to a 33MHz base clock instead of the default 66MHz. This
110 were previously running at 66MHz. If you want to use a 33MHz PCI card,
112 to flash prior to powering down the board and inserting the 33MHz PCI
116 default 66MHz. This has been tested with an intel PCI-X e1000 card.
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| /external/u-boot/board/freescale/ls1012afrdm/ |
| D | README | 22 to 108/54 MHz
38 - 25 MHz crystal for LS1012A
39 - 8 MHz Crystal for K20
40 - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | st,stm32h7-rcc.txt | 104 - 0: Wide VCO range:192 to 836 MHz
105 - 1: Medium VCO range:150 to 420 MHz
108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
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