| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 1 //===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
10 // MIMG-specific encoding families to distinguish between semantically
90 class MIMG <dag outs, string dns = "">
95 let MIMG = 1;
118 let FilterClass = "MIMG";
137 : MIMG <(outs dst_rc:$vdata), dns>,
189 : MIMG <(outs), dns>,
244 : MIMG <(outs data_rc:$vdst), !if(enableDasm, dns, "")> {
313 : MIMG <(outs dst_rc:$vdata), dns>,
439 // MIMG Instructions
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| D | SIInstrFormats.td | 52 field bit MIMG = 0;
147 let TSFlags{19} = MIMG;
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| D | SIDefines.h | 49 MIMG = 1 << 19, enumerator
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| D | SIInstrInfo.h | 439 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
443 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 44 MIMG = 11 variable in Format
100 elif self == Format.MIMG:
1372 opcode(name, code, code, code, Format.MIMG)
1374 opcode("image_msaa_load", -1, -1, 0x80, Format.MIMG) #GFX10.3+
1398 opcode(name, gfx7, gfx89, gfx7, Format.MIMG, is_atomic = True)
1444 opcode(name, code, code, code, Format.MIMG)
1477 opcode(name, code, code, code, Format.MIMG)
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| D | aco_insert_waitcnt.cpp | 418 …bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->op… in check_instr()
816 case Format::MIMG: in gen()
821 …bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->op… in gen()
827 instr->format != Format::MIMG && in gen()
833 instr->format == Format::MIMG && in gen()
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| D | aco_opt_value_numbering.cpp | 107 case Format::MIMG: in operator ()()
308 case Format::MIMG: { in operator ()()
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| D | aco_ir.cpp | 144 case Format::MIMG: in get_sync_info()
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| D | aco_validate.cpp | 214 (flat && i == 1) || (instr->format == Format::MIMG && i == 1) || in validate_ir()
437 case Format::MIMG: { in validate_ir()
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| D | README-ISA.md | 76 ## MIMG opcodes on GFX8/GCN3
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| D | aco_ir.h | 85 MIMG = 11, enumerator
939 format == Format::MIMG; in isVMEM()
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| D | aco_print_ir.cpp | 389 case Format::MIMG: { in print_instr_format_specific()
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| D | aco_insert_NOPs.cpp | 499 bool consider_mimg = instr->format == Format::MIMG && in handle_instruction_gfx6()
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| D | aco_assembler.cpp | 430 case Format::MIMG: { in emit_instruction()
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| D | aco_insert_exec_mask.cpp | 142 } else if (instr->format == Format::MIMG) { in needs_exact()
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| D | aco_instruction_selection.cpp | 5636 …nstruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)}; in adjust_sample_index_using_fmask()
5831 … aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)}; in visit_image_load()
5908 … aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)}; in visit_image_store()
6035 …aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, ret… in visit_image_atomic()
6105 …ion> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)}; in visit_image_size()
8923 …tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)); in visit_tex()
8963 …tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)); in visit_tex()
9112 tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1)); in visit_tex()
9253 tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)); in visit_tex()
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| D | aco_register_allocation.cpp | 2127 } else if (instr->format == Format::MIMG && in register_allocation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1105 // MIMG Instructions
2524 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2533 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2534 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2535 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2536 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2537 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2541 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2550 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2551 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
[all …]
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| D | SIInstrFormats.td | 42 field bits<1> MIMG = 0;
78 let TSFlags{20} = MIMG;
729 class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
734 let MIMG = 1;
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| D | SIDefines.h | 39 MIMG = 1 << 20, enumerator
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| D | SIInstrInfo.h | 312 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
316 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 255 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { in getInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2383 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDataSize()
2416 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGAtomicDMask()
2455 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGR128()
2471 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGD16()
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 227 MIMG Modifiers
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 448 bit DA = 0; // DA bit in MIMG encoding
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