1//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// MIMG-specific encoding families to distinguish between semantically 11// equivalent machine instructions with different encoding. 12// 13// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8) 14// - MIMGEncGfx8: encoding introduced with gfx8 for atomics 15class MIMGEncoding; 16 17def MIMGEncGfx6 : MIMGEncoding; 18def MIMGEncGfx8 : MIMGEncoding; 19 20def MIMGEncoding : GenericEnum { 21 let FilterClass = "MIMGEncoding"; 22} 23 24// Represent an ISA-level opcode, independent of the encoding and the 25// vdata/vaddr size. 26class MIMGBaseOpcode { 27 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME); 28 bit Store = 0; 29 bit Atomic = 0; 30 bit AtomicX2 = 0; // (f)cmpswap 31 bit Sampler = 0; 32 bits<8> NumExtraArgs = 0; 33 bit Gradients = 0; 34 bit Coordinates = 1; 35 bit LodOrClampOrMip = 0; 36 bit HasD16 = 0; 37} 38 39def MIMGBaseOpcode : GenericEnum { 40 let FilterClass = "MIMGBaseOpcode"; 41} 42 43def MIMGBaseOpcodesTable : GenericTable { 44 let FilterClass = "MIMGBaseOpcode"; 45 let CppTypeName = "MIMGBaseOpcodeInfo"; 46 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", 47 "NumExtraArgs", "Gradients", "Coordinates", "LodOrClampOrMip", 48 "HasD16"]; 49 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 50 51 let PrimaryKey = ["BaseOpcode"]; 52 let PrimaryKeyName = "getMIMGBaseOpcodeInfo"; 53} 54 55def MIMGDim : GenericEnum { 56 let FilterClass = "AMDGPUDimProps"; 57} 58 59def MIMGDimInfoTable : GenericTable { 60 let FilterClass = "AMDGPUDimProps"; 61 let CppTypeName = "MIMGDimInfo"; 62 let Fields = ["Dim", "NumCoords", "NumGradients", "DA"]; 63 GenericEnum TypeOf_Dim = MIMGDim; 64 65 let PrimaryKey = ["Dim"]; 66 let PrimaryKeyName = "getMIMGDimInfo"; 67} 68 69class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> { 70 MIMGBaseOpcode L = l; 71 MIMGBaseOpcode LZ = lz; 72} 73 74def MIMGLZMappingTable : GenericTable { 75 let FilterClass = "MIMGLZMapping"; 76 let CppTypeName = "MIMGLZMappingInfo"; 77 let Fields = ["L", "LZ"]; 78 GenericEnum TypeOf_L = MIMGBaseOpcode; 79 GenericEnum TypeOf_LZ = MIMGBaseOpcode; 80 81 let PrimaryKey = ["L"]; 82 let PrimaryKeyName = "getMIMGLZMappingInfo"; 83} 84 85class mimg <bits<7> si, bits<7> vi = si> { 86 field bits<7> SI = si; 87 field bits<7> VI = vi; 88} 89 90class MIMG <dag outs, string dns = ""> 91 : InstSI <outs, (ins), "", []> { 92 93 let VM_CNT = 1; 94 let EXP_CNT = 1; 95 let MIMG = 1; 96 let Uses = [EXEC]; 97 let mayLoad = 1; 98 let mayStore = 0; 99 let hasPostISelHook = 1; 100 let SchedRW = [WriteVMEM]; 101 let UseNamedOperandTable = 1; 102 let hasSideEffects = 0; // XXX ???? 103 104 let SubtargetPredicate = isGCN; 105 let DecoderNamespace = dns; 106 let isAsmParserOnly = !if(!eq(dns,""), 1, 0); 107 let AsmMatchConverter = "cvtMIMG"; 108 let usesCustomInserter = 1; 109 110 Instruction Opcode = !cast<Instruction>(NAME); 111 MIMGBaseOpcode BaseOpcode; 112 MIMGEncoding MIMGEncoding = MIMGEncGfx6; 113 bits<8> VDataDwords; 114 bits<8> VAddrDwords; 115} 116 117def MIMGInfoTable : GenericTable { 118 let FilterClass = "MIMG"; 119 let CppTypeName = "MIMGInfo"; 120 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 121 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 122 GenericEnum TypeOf_MIMGEncoding = MIMGEncoding; 123 124 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"]; 125 let PrimaryKeyName = "getMIMGOpcodeHelper"; 126} 127 128def getMIMGInfo : SearchIndex { 129 let Table = MIMGInfoTable; 130 let Key = ["Opcode"]; 131} 132 133class MIMG_NoSampler_Helper <bits<7> op, string asm, 134 RegisterClass dst_rc, 135 RegisterClass addr_rc, 136 string dns=""> 137 : MIMG <(outs dst_rc:$vdata), dns>, 138 MIMGe<op> { 139 let ssamp = 0; 140 let d16 = !if(BaseOpcode.HasD16, ?, 0); 141 142 let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc, 143 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 144 R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 145 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 146 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 147 #!if(BaseOpcode.HasD16, "$d16", ""); 148} 149 150multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm, 151 RegisterClass dst_rc, 152 bit enableDisasm> { 153 let VAddrDwords = 1 in 154 def NAME # _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, 155 !if(enableDisasm, "AMDGPU", "")>; 156 let VAddrDwords = 2 in 157 def NAME # _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; 158 let VAddrDwords = 3 in 159 def NAME # _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; 160 let VAddrDwords = 4 in 161 def NAME # _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; 162} 163 164multiclass MIMG_NoSampler <bits<7> op, string asm, bit has_d16, bit mip = 0, 165 bit isResInfo = 0> { 166 def "" : MIMGBaseOpcode { 167 let Coordinates = !if(isResInfo, 0, 1); 168 let LodOrClampOrMip = mip; 169 let HasD16 = has_d16; 170 } 171 172 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), 173 mayLoad = !if(isResInfo, 0, 1) in { 174 let VDataDwords = 1 in 175 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>; 176 let VDataDwords = 2 in 177 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>; 178 let VDataDwords = 3 in 179 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>; 180 let VDataDwords = 4 in 181 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>; 182 } 183} 184 185class MIMG_Store_Helper <bits<7> op, string asm, 186 RegisterClass data_rc, 187 RegisterClass addr_rc, 188 string dns = ""> 189 : MIMG <(outs), dns>, 190 MIMGe<op> { 191 let ssamp = 0; 192 let d16 = !if(BaseOpcode.HasD16, ?, 0); 193 194 let mayLoad = 0; 195 let mayStore = 1; 196 let hasSideEffects = 0; 197 let hasPostISelHook = 0; 198 let DisableWQM = 1; 199 200 let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 201 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 202 R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 203 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 204 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 205 #!if(BaseOpcode.HasD16, "$d16", ""); 206} 207 208multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm, 209 RegisterClass data_rc, 210 bit enableDisasm> { 211 let VAddrDwords = 1 in 212 def NAME # _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, 213 !if(enableDisasm, "AMDGPU", "")>; 214 let VAddrDwords = 2 in 215 def NAME # _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>; 216 let VAddrDwords = 3 in 217 def NAME # _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>; 218 let VAddrDwords = 4 in 219 def NAME # _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>; 220} 221 222multiclass MIMG_Store <bits<7> op, string asm, bit has_d16, bit mip = 0> { 223 def "" : MIMGBaseOpcode { 224 let Store = 1; 225 let LodOrClampOrMip = mip; 226 let HasD16 = has_d16; 227 } 228 229 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 230 let VDataDwords = 1 in 231 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; 232 let VDataDwords = 2 in 233 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>; 234 let VDataDwords = 3 in 235 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>; 236 let VDataDwords = 4 in 237 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>; 238 } 239} 240 241class MIMG_Atomic_Helper <string asm, RegisterClass data_rc, 242 RegisterClass addr_rc, string dns="", 243 bit enableDasm = 0> 244 : MIMG <(outs data_rc:$vdst), !if(enableDasm, dns, "")> { 245 let mayLoad = 1; 246 let mayStore = 1; 247 let hasSideEffects = 1; // FIXME: Remove this 248 let hasPostISelHook = 0; 249 let DisableWQM = 1; 250 let Constraints = "$vdst = $vdata"; 251 let AsmMatchConverter = "cvtMIMGAtomic"; 252 253 let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, 254 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 255 R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da); 256 let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"; 257} 258 259multiclass MIMG_Atomic_Helper_m <mimg op, string asm, RegisterClass data_rc, 260 RegisterClass addr_rc, bit enableDasm = 0> { 261 let ssamp = 0, d16 = 0 in { 262 def _si : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "SICI", enableDasm>, 263 SIMCInstr<NAME, SIEncodingFamily.SI>, 264 MIMGe<op.SI> { 265 let AssemblerPredicates = [isSICI]; 266 let DisableDecoder = DisableSIDecoder; 267 } 268 269 def _vi : MIMG_Atomic_Helper<asm, data_rc, addr_rc, "VI", enableDasm>, 270 SIMCInstr<NAME, SIEncodingFamily.VI>, 271 MIMGe<op.VI> { 272 let AssemblerPredicates = [isVI]; 273 let DisableDecoder = DisableVIDecoder; 274 let MIMGEncoding = MIMGEncGfx8; 275 } 276 } 277} 278 279multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm, 280 RegisterClass data_rc, 281 bit enableDasm = 0> { 282 // _V* variants have different address size, but the size is not encoded. 283 // So only one variant can be disassembled. V1 looks the safest to decode. 284 let VAddrDwords = 1 in 285 defm _V1 : MIMG_Atomic_Helper_m <op, asm, data_rc, VGPR_32, enableDasm>; 286 let VAddrDwords = 2 in 287 defm _V2 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_64>; 288 let VAddrDwords = 3 in 289 defm _V3 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_96>; 290 let VAddrDwords = 4 in 291 defm _V4 : MIMG_Atomic_Helper_m <op, asm, data_rc, VReg_128>; 292} 293 294multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics 295 def "" : MIMGBaseOpcode { 296 let Atomic = 1; 297 let AtomicX2 = isCmpSwap; 298 } 299 300 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in { 301 // _V* variants have different dst size, but the size is encoded implicitly, 302 // using dmask and tfe. Only 32-bit variant is registered with disassembler. 303 // Other variants are reconstructed by disassembler using dmask and tfe. 304 let VDataDwords = !if(isCmpSwap, 2, 1) in 305 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>; 306 let VDataDwords = !if(isCmpSwap, 4, 2) in 307 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>; 308 } 309} 310 311class MIMG_Sampler_Helper <bits<7> op, string asm, RegisterClass dst_rc, 312 RegisterClass src_rc, string dns=""> 313 : MIMG <(outs dst_rc:$vdata), dns>, 314 MIMGe<op> { 315 let d16 = !if(BaseOpcode.HasD16, ?, 0); 316 317 let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, 318 DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc, 319 R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 320 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins))); 321 let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da" 322 #!if(BaseOpcode.HasD16, "$d16", ""); 323} 324 325class MIMGAddrSize<int dw, bit enable_disasm> { 326 int NumWords = dw; 327 328 RegisterClass RegClass = !if(!le(NumWords, 0), ?, 329 !if(!eq(NumWords, 1), VGPR_32, 330 !if(!eq(NumWords, 2), VReg_64, 331 !if(!eq(NumWords, 3), VReg_96, 332 !if(!eq(NumWords, 4), VReg_128, 333 !if(!le(NumWords, 8), VReg_256, 334 !if(!le(NumWords, 16), VReg_512, ?))))))); 335 336 // Whether the instruction variant with this vaddr size should be enabled for 337 // the auto-generated disassembler. 338 bit Disassemble = enable_disasm; 339} 340 341// Return whether a value inside the range [min, max] (endpoints inclusive) 342// is in the given list. 343class isRangeInList<int min, int max, list<int> lst> { 344 bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max)))); 345} 346 347class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> { 348 list<MIMGAddrSize> List = lst; 349 int Min = min; 350} 351 352class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> { 353 // List of all possible numbers of address words, taking all combinations of 354 // A16 and image dimension into account (note: no MSAA, since this is for 355 // sample/gather ops). 356 list<int> AllNumAddrWords = 357 !foreach(dw, !if(sample.Gradients, 358 !if(!eq(sample.LodOrClamp, ""), 359 [2, 3, 4, 5, 6, 7, 9], 360 [2, 3, 4, 5, 7, 8, 10]), 361 !if(!eq(sample.LodOrClamp, ""), 362 [1, 2, 3], 363 [1, 2, 3, 4])), 364 !add(dw, !size(sample.ExtraAddrArgs))); 365 366 // Generate machine instructions based on possible register classes for the 367 // required numbers of address words. The disassembler defaults to the 368 // smallest register class. 369 list<MIMGAddrSize> MachineInstrs = 370 !foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw, 371 !if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret, 372 MIMGAddrSizes_tmp< 373 !listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]), 374 !if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords 375 lhs)).List; 376} 377 378multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, 379 AMDGPUSampleVariant sample, RegisterClass dst_rc, 380 bit enableDisasm = 0> { 381 foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in { 382 let VAddrDwords = addr.NumWords in 383 def _V # addr.NumWords 384 : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, 385 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; 386 } 387} 388 389class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample> 390 : MIMGBaseOpcode { 391 let Sampler = 1; 392 let NumExtraArgs = !size(sample.ExtraAddrArgs); 393 let Gradients = sample.Gradients; 394 let LodOrClampOrMip = !ne(sample.LodOrClamp, ""); 395} 396 397multiclass MIMG_Sampler <bits<7> op, AMDGPUSampleVariant sample, bit wqm = 0, 398 bit isGetLod = 0, 399 string asm = "image_sample"#sample.LowerCaseMod> { 400 def "" : MIMG_Sampler_BaseOpcode<sample> { 401 let HasD16 = !if(isGetLod, 0, 1); 402 } 403 404 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 405 mayLoad = !if(isGetLod, 0, 1) in { 406 let VDataDwords = 1 in 407 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>; 408 let VDataDwords = 2 in 409 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; 410 let VDataDwords = 3 in 411 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>; 412 let VDataDwords = 4 in 413 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>; 414 } 415} 416 417multiclass MIMG_Sampler_WQM <bits<7> op, AMDGPUSampleVariant sample> 418 : MIMG_Sampler<op, sample, 1>; 419 420multiclass MIMG_Gather <bits<7> op, AMDGPUSampleVariant sample, bit wqm = 0, 421 string asm = "image_gather4"#sample.LowerCaseMod> { 422 def "" : MIMG_Sampler_BaseOpcode<sample> { 423 let HasD16 = 1; 424 } 425 426 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm, 427 Gather4 = 1, hasPostISelHook = 0 in { 428 let VDataDwords = 2 in 429 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */ 430 let VDataDwords = 4 in 431 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>; 432 } 433} 434 435multiclass MIMG_Gather_WQM <bits<7> op, AMDGPUSampleVariant sample> 436 : MIMG_Gather<op, sample, 1>; 437 438//===----------------------------------------------------------------------===// 439// MIMG Instructions 440//===----------------------------------------------------------------------===// 441defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>; 442defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>; 443defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>; 444defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>; 445defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>; 446defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>; 447defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>; 448defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>; 449defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>; 450defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>; 451 452defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>; 453 454defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">; 455defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>; 456defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">; 457defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">; 458//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI 459defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">; 460defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">; 461defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">; 462defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">; 463defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">; 464defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">; 465defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">; 466defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">; 467defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">; 468//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI 469//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI 470//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI 471defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>; 472defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>; 473defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>; 474defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>; 475defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>; 476defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>; 477defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>; 478defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>; 479defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>; 480defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>; 481defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>; 482defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>; 483defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>; 484defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>; 485defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>; 486defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>; 487defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>; 488defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>; 489defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>; 490defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>; 491defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>; 492defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>; 493defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>; 494defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>; 495defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>; 496defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>; 497defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>; 498defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>; 499defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>; 500defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>; 501defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>; 502defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>; 503defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>; 504defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>; 505defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>; 506defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>; 507defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>; 508defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>; 509defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>; 510defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>; 511defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>; 512defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>; 513defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>; 514defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>; 515defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>; 516defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>; 517defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>; 518defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>; 519defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>; 520defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>; 521defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>; 522defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>; 523defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>; 524defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>; 525defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>; 526defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>; 527 528defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 1, "image_get_lod">; 529 530defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>; 531defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>; 532defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>; 533defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>; 534defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>; 535defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>; 536defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>; 537defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>; 538//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 539//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 540 541/********** ========================================= **********/ 542/********** Table of dimension-aware image intrinsics **********/ 543/********** ========================================= **********/ 544 545class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> { 546 Intrinsic Intr = I; 547 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod)); 548 AMDGPUDimProps Dim = I.P.Dim; 549} 550 551def ImageDimIntrinsicTable : GenericTable { 552 let FilterClass = "ImageDimIntrinsicInfo"; 553 let Fields = ["Intr", "BaseOpcode", "Dim"]; 554 GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode; 555 GenericEnum TypeOf_Dim = MIMGDim; 556 557 let PrimaryKey = ["Intr"]; 558 let PrimaryKeyName = "getImageDimIntrinsicInfo"; 559 let PrimaryKeyEarlyOut = 1; 560} 561 562foreach intr = !listconcat(AMDGPUImageDimIntrinsics, 563 AMDGPUImageDimAtomicIntrinsics) in { 564 def : ImageDimIntrinsicInfo<intr>; 565} 566 567// L to LZ Optimization Mapping 568def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>; 569def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>; 570def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>; 571def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>; 572def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>; 573def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>; 574def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>; 575def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>; 576