/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | arm64-aliases.s | 150 ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias. 164 ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is 179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV 180 ; corresponds to the MOVZ version. 196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In 197 ; both cases MOVZ/MOVN are preferred.
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/external/llvm/test/MC/AArch64/ |
D | arm64-aliases.s | 150 ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias. 164 ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is 179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV 180 ; corresponds to the MOVZ version. 196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In 197 ; both cases MOVZ/MOVN are preferred.
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/external/u-boot/arch/mips/include/asm/ |
D | asm.h | 189 #define MOVZ(rd, rs, rt) \ macro 205 #define MOVZ(rd, rs, rt) \ macro 217 #define MOVZ(rd, rs, rt) \ macro
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/external/pcre/dist2/src/sljit/ |
D | sljitNativeARM_64.c | 107 #define MOVZ 0xd2800000 macro 148 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in emit_imm64_const() 157 SLJIT_ASSERT((inst[0] & 0xffe00000) == MOVZ && (inst[1] & 0xffe00000) == (MOVK | (1 << 21))); in modify_imm64_const() 158 inst[0] = MOVZ | dst | ((new_imm & 0xffff) << 5); in modify_imm64_const() 316 buf_ptr[0] = MOVZ | dst | ((addr & 0xffff) << 5); in sljit_generate_code() 464 return push_inst(compiler, MOVZ | RD(dst) | (imm << 5)); in load_immediate() 471 return push_inst(compiler, MOVZ | RD(dst) | ((imm >> 16) << 5) | (1 << 21)); in load_immediate() 481 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in load_immediate() 536 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((simm & 0xffff) << 5) | (i << 21))); in load_immediate() 953 FAIL_IF(push_inst(compiler, MOVZ | RD(TMP_REG2) | (((local_size >> 12) - 1) << 5))); in sljit_emit_enter()
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D | sljitNativeMIPS_common.c | 263 #define MOVZ (HI(0) | LO(10)) macro 2111 ins = MOVZ | TA(EQUAL_FLAG); in sljit_emit_cmov() 2130 ins = MOVZ | TA(OTHER_FLAG); in sljit_emit_cmov() 2145 ins = MOVZ | TA(OTHER_FLAG); in sljit_emit_cmov()
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-movi.ll | 43 ; Tests for MOVZ with MOVK.
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/external/llvm/lib/Target/AArch64/ |
D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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D | AArch64SchedCyclone.td | 109 // MOVZ Rd, #0 129 // MOVN,MOVZ,MOVK
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D | AArch64InstrInfo.td | 446 defm MOVZ : MoveImmediate<0b10, "movz">; 499 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; 500 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; 502 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; 503 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; 504 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; 505 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; 569 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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D | AArch64SchedCyclone.td | 111 // MOVZ Rd, #0 131 // MOVN,MOVZ,MOVK
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D | AArch64InstrInfo.td | 642 defm MOVZ : MoveImmediate<0b10, "movz">; 695 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; 696 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; 698 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; 699 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; 700 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; 701 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; 768 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
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D | AArch64SchedFalkorDetails.td | 1236 def : InstRW<[FalkorWr_MOVZ], (instregex "^MOVZ(W|X)i$")>;
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/external/v8/src/codegen/mips/ |
D | constants-mips.h | 500 MOVZ = ((1U << 3) + 2), enumerator 1274 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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D | assembler-mips.cc | 2310 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
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/external/v8/src/codegen/mips64/ |
D | constants-mips64.h | 482 MOVZ = ((1U << 3) + 2), enumerator 1321 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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/external/v8/src/codegen/arm64/ |
D | constants-arm64.h | 657 MOVZ = 0x40000000, enumerator 661 MOVZ_w = MoveWideImmediateFixed | MOVZ, 662 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
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D | assembler-arm64.h | 904 MoveWide(rd, imm, shift, MOVZ);
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | arm64-movi.ll | 74 ; Tests for MOVZ with MOVK.
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/external/vixl/src/aarch64/ |
D | constants-aarch64.h | 666 MOVZ = 0x40000000, enumerator 670 MOVZ_w = MoveWideImmediateFixed | MOVZ, 671 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
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D | assembler-aarch64.h | 2137 MoveWide(rd, imm, shift, MOVZ);
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/external/v8/src/diagnostics/mips/ |
D | disasm-mips.cc | 1403 case MOVZ: in DecodeTypeRegisterSPECIAL()
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/external/v8/src/diagnostics/mips64/ |
D | disasm-mips64.cc | 1636 case MOVZ: in DecodeTypeRegisterSPECIAL()
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/external/capstone/arch/X86/ |
D | X86GenAsmWriter1_reduce.inc | 2400 // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ...
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D | X86GenAsmWriter_reduce.inc | 2469 // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ...
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