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Searched refs:MOVZ (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-aliases.s150 ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias.
164 ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is
179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
180 ; corresponds to the MOVZ version.
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
/external/llvm/test/MC/AArch64/
Darm64-aliases.s150 ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias.
164 ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is
179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
180 ; corresponds to the MOVZ version.
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
/external/u-boot/arch/mips/include/asm/
Dasm.h189 #define MOVZ(rd, rs, rt) \ macro
205 #define MOVZ(rd, rs, rt) \ macro
217 #define MOVZ(rd, rs, rt) \ macro
/external/pcre/dist2/src/sljit/
DsljitNativeARM_64.c107 #define MOVZ 0xd2800000 macro
148 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in emit_imm64_const()
157 SLJIT_ASSERT((inst[0] & 0xffe00000) == MOVZ && (inst[1] & 0xffe00000) == (MOVK | (1 << 21))); in modify_imm64_const()
158 inst[0] = MOVZ | dst | ((new_imm & 0xffff) << 5); in modify_imm64_const()
316 buf_ptr[0] = MOVZ | dst | ((addr & 0xffff) << 5); in sljit_generate_code()
464 return push_inst(compiler, MOVZ | RD(dst) | (imm << 5)); in load_immediate()
471 return push_inst(compiler, MOVZ | RD(dst) | ((imm >> 16) << 5) | (1 << 21)); in load_immediate()
481 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in load_immediate()
536 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((simm & 0xffff) << 5) | (i << 21))); in load_immediate()
953 FAIL_IF(push_inst(compiler, MOVZ | RD(TMP_REG2) | (((local_size >> 12) - 1) << 5))); in sljit_emit_enter()
DsljitNativeMIPS_common.c263 #define MOVZ (HI(0) | LO(10)) macro
2111 ins = MOVZ | TA(EQUAL_FLAG); in sljit_emit_cmov()
2130 ins = MOVZ | TA(OTHER_FLAG); in sljit_emit_cmov()
2145 ins = MOVZ | TA(OTHER_FLAG); in sljit_emit_cmov()
/external/llvm/test/CodeGen/AArch64/
Darm64-movi.ll43 ; Tests for MOVZ with MOVK.
/external/llvm/lib/Target/AArch64/
DAArch64Schedule.td21 def WriteImm : SchedWrite; // MOVN, MOVZ
DAArch64SchedCyclone.td109 // MOVZ Rd, #0
129 // MOVN,MOVZ,MOVK
DAArch64InstrInfo.td446 defm MOVZ : MoveImmediate<0b10, "movz">;
499 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
500 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
502 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
503 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
504 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
505 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
569 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64Schedule.td21 def WriteImm : SchedWrite; // MOVN, MOVZ
DAArch64SchedCyclone.td111 // MOVZ Rd, #0
131 // MOVN,MOVZ,MOVK
DAArch64InstrInfo.td642 defm MOVZ : MoveImmediate<0b10, "movz">;
695 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
696 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
698 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
699 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
700 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
701 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
768 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
DAArch64SchedFalkorDetails.td1236 def : InstRW<[FalkorWr_MOVZ], (instregex "^MOVZ(W|X)i$")>;
/external/v8/src/codegen/mips/
Dconstants-mips.h500 MOVZ = ((1U << 3) + 2), enumerator
1274 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
Dassembler-mips.cc2310 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
/external/v8/src/codegen/mips64/
Dconstants-mips64.h482 MOVZ = ((1U << 3) + 2), enumerator
1321 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
/external/v8/src/codegen/arm64/
Dconstants-arm64.h657 MOVZ = 0x40000000, enumerator
661 MOVZ_w = MoveWideImmediateFixed | MOVZ,
662 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
Dassembler-arm64.h904 MoveWide(rd, imm, shift, MOVZ);
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-movi.ll74 ; Tests for MOVZ with MOVK.
/external/vixl/src/aarch64/
Dconstants-aarch64.h666 MOVZ = 0x40000000, enumerator
670 MOVZ_w = MoveWideImmediateFixed | MOVZ,
671 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
Dassembler-aarch64.h2137 MoveWide(rd, imm, shift, MOVZ);
/external/v8/src/diagnostics/mips/
Ddisasm-mips.cc1403 case MOVZ: in DecodeTypeRegisterSPECIAL()
/external/v8/src/diagnostics/mips64/
Ddisasm-mips64.cc1636 case MOVZ: in DecodeTypeRegisterSPECIAL()
/external/capstone/arch/X86/
DX86GenAsmWriter1_reduce.inc2400 // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ...
DX86GenAsmWriter_reduce.inc2469 // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ...

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