| /external/arm-trusted-firmware/plat/mediatek/mt8173/ |
| D | power_tracer.c | 19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
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| D | scu.c | 14 if (mpidr & MPIDR_CLUSTER_MASK) in disable_scu()
24 if (mpidr & MPIDR_CLUSTER_MASK) in enable_scu()
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| D | plat_pm.c | 108 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
263 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_power_domain_on()
329 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_power_domain_suspend()
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/ |
| D | power_tracer.c | 19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
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| D | scu.c | 14 if (mpidr & MPIDR_CLUSTER_MASK) in disable_scu()
24 if (mpidr & MPIDR_CLUSTER_MASK) in enable_scu()
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| D | plat_pm.c | 66 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
254 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_affinst_on()
327 cluster_id = mpidr & MPIDR_CLUSTER_MASK; in plat_affinst_suspend()
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/ |
| D | spm_mcdi.c | 307 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_enter()
358 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_leave()
408 unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
440 unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; in spm_mcdi_clear_cputop_pwrctrl_for_cluster_on()
495 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_mcdi_finish_for_on_state()
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| D | spm_hotplug.c | 240 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_hotplug_on()
261 linear_id = ((mpidr & MPIDR_CLUSTER_MASK) >> 6) | in spm_hotplug_off()
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| /external/arm-trusted-firmware/plat/rockchip/common/aarch32/ |
| D | plat_helpers.S | 43 and r0, r0, #MPIDR_CLUSTER_MASK
69 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
102 and r6, r0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/rockchip/common/aarch64/ |
| D | plat_helpers.S | 57 and x0, x0, #MPIDR_CLUSTER_MASK
79 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
106 and x20, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/aarch64/ |
| D | plat_helpers.S | 16 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
31 and x0, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/ |
| D | plat_helpers.S | 31 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
46 and x0, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| D | hikey960_pm.c | 65 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_on()
96 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_off()
185 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend()
261 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend_finish()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | scu.c | 21 switch (mpidr & MPIDR_CLUSTER_MASK) { in disable_scu()
42 switch (mpidr & MPIDR_CLUSTER_MASK) { in enable_scu()
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/ |
| D | plat_helpers.S | 49 and x1, x1, #MPIDR_CLUSTER_MASK
91 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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| /external/arm-trusted-firmware/plat/rpi/rpi3/aarch64/ |
| D | plat_helpers.S | 44 and x0, x0, #MPIDR_CLUSTER_MASK
58 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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| /external/arm-trusted-firmware/plat/qemu/common/aarch64/ |
| D | plat_helpers.S | 34 and x0, x0, #MPIDR_CLUSTER_MASK
48 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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| /external/arm-trusted-firmware/plat/imx/common/ |
| D | imx8_helpers.S | 72 and x0, x0, #MPIDR_CLUSTER_MASK
84 and x0, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/qemu/common/aarch32/ |
| D | plat_helpers.S | 35 and r0, r0, #MPIDR_CLUSTER_MASK
49 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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| /external/arm-trusted-firmware/plat/rpi/rpi4/aarch64/ |
| D | plat_helpers.S | 46 and x0, x0, #MPIDR_CLUSTER_MASK
60 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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| /external/arm-trusted-firmware/plat/intel/soc/common/aarch64/ |
| D | plat_helpers.S | 50 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
64 and x0, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/ |
| D | tegra_helpers.S | 141 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
156 and x0, x0, #MPIDR_CLUSTER_MASK
188 and x0, x0, #MPIDR_CLUSTER_MASK
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| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | plat_versal.c | 12 if (mpidr & MPIDR_CLUSTER_MASK) in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
| D | plat_zynqmp.c | 12 if (mpidr & MPIDR_CLUSTER_MASK) in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/hisilicon/poplar/ |
| D | plat_topology.c | 26 if (mpidr & MPIDR_CLUSTER_MASK) in plat_core_pos_by_mpidr()
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