1/* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <platform_def.h> 11 12 .globl plat_my_core_pos 13 .globl plat_get_my_entrypoint 14 .globl platform_mem_init 15 .globl plat_qemu_calc_core_pos 16 .globl plat_crash_console_init 17 .globl plat_crash_console_putc 18 .globl plat_crash_console_flush 19 .globl plat_secondary_cold_boot_setup 20 .globl plat_get_my_entrypoint 21 .globl plat_is_my_cpu_primary 22 23func plat_my_core_pos 24 mrs x0, mpidr_el1 25 b plat_qemu_calc_core_pos 26endfunc plat_my_core_pos 27 28/* 29 * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); 30 * With this function: CorePos = (ClusterId * 4) + CoreId 31 */ 32func plat_qemu_calc_core_pos 33 and x1, x0, #MPIDR_CPU_MASK 34 and x0, x0, #MPIDR_CLUSTER_MASK 35 add x0, x1, x0, LSR #6 36 ret 37endfunc plat_qemu_calc_core_pos 38 39 /* ----------------------------------------------------- 40 * unsigned int plat_is_my_cpu_primary (void); 41 * 42 * Find out whether the current cpu is the primary 43 * cpu. 44 * ----------------------------------------------------- 45 */ 46func plat_is_my_cpu_primary 47 mrs x0, mpidr_el1 48 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 49 cmp x0, #QEMU_PRIMARY_CPU 50 cset w0, eq 51 ret 52endfunc plat_is_my_cpu_primary 53 54 /* ----------------------------------------------------- 55 * void plat_secondary_cold_boot_setup (void); 56 * 57 * This function performs any platform specific actions 58 * needed for a secondary cpu after a cold reset e.g 59 * mark the cpu's presence, mechanism to place it in a 60 * holding pen etc. 61 * ----------------------------------------------------- 62 */ 63func plat_secondary_cold_boot_setup 64 /* Calculate address of our hold entry */ 65 bl plat_my_core_pos 66 lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT 67 mov_imm x2, PLAT_QEMU_HOLD_BASE 68 69 /* Wait until we have a go */ 70poll_mailbox: 71 ldr x1, [x2, x0] 72 cbz x1, 1f 73 74 /* Clear the mailbox again ready for next time. */ 75 mov x1, #PLAT_QEMU_HOLD_STATE_WAIT 76 str x1, [x2, x0] 77 78 /* Jump to the provided entrypoint. */ 79 mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE 80 ldr x1, [x0] 81 br x1 821: 83 wfe 84 b poll_mailbox 85endfunc plat_secondary_cold_boot_setup 86 87func plat_get_my_entrypoint 88 /* TODO support warm boot */ 89 mov x0, #0 90 ret 91endfunc plat_get_my_entrypoint 92 93func platform_mem_init 94 ret 95endfunc platform_mem_init 96 97 /* --------------------------------------------- 98 * int plat_crash_console_init(void) 99 * Function to initialize the crash console 100 * without a C Runtime to print crash report. 101 * Clobber list : x0, x1, x2 102 * --------------------------------------------- 103 */ 104func plat_crash_console_init 105 mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 106 mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ 107 mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE 108 b console_pl011_core_init 109endfunc plat_crash_console_init 110 111 /* --------------------------------------------- 112 * int plat_crash_console_putc(int c) 113 * Function to print a character on the crash 114 * console without a C Runtime. 115 * Clobber list : x1, x2 116 * --------------------------------------------- 117 */ 118func plat_crash_console_putc 119 mov_imm x1, PLAT_QEMU_CRASH_UART_BASE 120 b console_pl011_core_putc 121endfunc plat_crash_console_putc 122 123 /* --------------------------------------------- 124 * int plat_crash_console_flush(int c) 125 * Function to force a write of all buffered 126 * data that hasn't been output. 127 * Out : return -1 on error else return 0. 128 * Clobber list : x0, x1 129 * --------------------------------------------- 130 */ 131func plat_crash_console_flush 132 mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 133 b console_pl011_core_flush 134endfunc plat_crash_console_flush 135 136