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Searched refs:MRM6r (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h344 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 enumerator
730 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp945 case X86II::MRM6r: case X86II::MRM7r: { in EmitVEXOpcodePrefix()
1095 case X86II::MRM6r: case X86II::MRM7r: in DetermineREXPrefix()
1489 case X86II::MRM6r: case X86II::MRM7r: in encodeInstruction()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
688 case X86II::MRM6r: case X86II::MRM7r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp872 case X86II::MRM6r: case X86II::MRM7r: { in EmitVEXOpcodePrefix()
1023 case X86II::MRM6r: case X86II::MRM7r: in DetermineREXPrefix()
1358 case X86II::MRM6r: case X86II::MRM7r: { in encodeInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h118 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, enumerator
DX86RecognizableInstr.cpp631 case X86Local::MRM6r: in emitInstructionSpecifier()
746 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
DX86FoldTablesEmitter.cpp421 (MemFormNum == X86Local::MRM6m && RegFormNum == X86Local::MRM6r) || in areOppositeForms()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
721 case X86Local::MRM6r: in emitInstructionSpecifier()
855 case X86Local::MRM6r: case X86Local::MRM7r: in emitDecodePath()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrMMX.td422 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
426 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
430 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
DX86InstrFPStack.td294 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
295 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
296 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
620 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), "fcomi\t$reg">;
621 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), "fcompi\t$reg">;
DX86InstrInfo.td1227 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
1229 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
1313 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
1889 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1892 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1895 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
2279 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2282 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2285 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2656 defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>;
[all …]
DX86InstrArithmetic.td282 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
285 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
288 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
292 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
1160 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
DX86InstrSystem.td428 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
DX86InstrFormats.td45 def MRM6r : Format<62>; def MRM7r : Format<63>;
/external/llvm/lib/Target/X86/
DX86InstrMMX.td488 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
491 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
494 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
DX86InstrFPStack.td287 def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">;
288 def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">;
289 def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">;
605 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg),
607 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg),
DX86InstrInfo.td1113 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1115 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1194 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1738 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1741 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1744 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2116 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2119 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2122 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2397 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
[all …]
DX86InstrArithmetic.td298 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
301 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
304 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
308 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
1195 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
DX86InstrSystem.td460 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
DX86InstrSSE.td4043 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4046 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4063 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4094 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4097 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4114 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4144 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4147 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4150 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
DX86InstrFormats.td32 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DTargetInstrInfo.td54 def MRM6r : Format<22>; def MRM7r : Format<23>;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DWritingAnLLVMBackend.rst1861 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data
/external/llvm/docs/
DWritingAnLLVMBackend.rst1821 case X86II::MRM6r: case X86II::MRM7r: // to hold extended opcode data

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