1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 instructions that are generally used in 11// privileged modes. These are not typically used by the compiler, but are 12// supported for the assembler and disassembler. 13// 14//===----------------------------------------------------------------------===// 15 16let SchedRW = [WriteSystem] in { 17let Defs = [RAX, RDX] in 18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB; 19 20let Defs = [RAX, RCX, RDX] in 21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB; 22 23// CPU flow control instructions 24 25let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in { 26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB; 27 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB; 28} 29 30def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>; 31def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB; 32 33// Interrupt and SysCall Instructions. 34let Uses = [EFLAGS] in 35 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>; 36 37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; 38} // SchedRW 39 40// The long form of "int $3" turns into int3 as a size optimization. 41// FIXME: This doesn't work because InstAlias can't match immediate constants. 42//def : InstAlias<"int\t$3", (INT3)>; 43 44let SchedRW = [WriteSystem] in { 45 46def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap", 47 [(int_x86_int imm:$trap)]>; 48 49 50def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; 51def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB; 52def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB, 53 Requires<[In64BitMode]>; 54 55def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; 56 57def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB; 58def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB, 59 Requires<[In64BitMode]>; 60} // SchedRW 61 62def : Pat<(debugtrap), 63 (INT3)>, Requires<[NotPS4]>; 64def : Pat<(debugtrap), 65 (INT (i8 0x41))>, Requires<[IsPS4]>; 66 67//===----------------------------------------------------------------------===// 68// Input/Output Instructions. 69// 70let SchedRW = [WriteSystem] in { 71let Defs = [AL], Uses = [DX] in 72def IN8rr : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>; 73let Defs = [AX], Uses = [DX] in 74def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>, 75 OpSize16; 76let Defs = [EAX], Uses = [DX] in 77def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>, 78 OpSize32; 79 80let Defs = [AL] in 81def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port), 82 "in{b}\t{$port, %al|al, $port}", []>; 83let Defs = [AX] in 84def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 85 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16; 86let Defs = [EAX] in 87def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port), 88 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32; 89 90let Uses = [DX, AL] in 91def OUT8rr : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>; 92let Uses = [DX, AX] in 93def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>, 94 OpSize16; 95let Uses = [DX, EAX] in 96def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>, 97 OpSize32; 98 99let Uses = [AL] in 100def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port), 101 "out{b}\t{%al, $port|$port, al}", []>; 102let Uses = [AX] in 103def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 104 "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16; 105let Uses = [EAX] in 106def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port), 107 "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32; 108 109} // SchedRW 110 111//===----------------------------------------------------------------------===// 112// Moves to and from debug registers 113 114let SchedRW = [WriteSystem] in { 115def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src), 116 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 117 Requires<[Not64BitMode]>; 118def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src), 119 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 120 Requires<[In64BitMode]>; 121 122def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src), 123 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 124 Requires<[Not64BitMode]>; 125def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src), 126 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 127 Requires<[In64BitMode]>; 128} // SchedRW 129 130//===----------------------------------------------------------------------===// 131// Moves to and from control registers 132 133let SchedRW = [WriteSystem] in { 134def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src), 135 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 136 Requires<[Not64BitMode]>; 137def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src), 138 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 139 Requires<[In64BitMode]>; 140 141def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src), 142 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB, 143 Requires<[Not64BitMode]>; 144def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src), 145 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB, 146 Requires<[In64BitMode]>; 147} // SchedRW 148 149//===----------------------------------------------------------------------===// 150// Segment override instruction prefixes 151 152let SchedRW = [WriteNop] in { 153def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>; 154def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>; 155def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>; 156def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>; 157def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>; 158def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>; 159} // SchedRW 160 161//===----------------------------------------------------------------------===// 162// Moves to and from segment registers. 163// 164 165let SchedRW = [WriteMove] in { 166def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src), 167 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 168def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src), 169 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 170def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src), 171 "mov{q}\t{$src, $dst|$dst, $src}", []>; 172let mayStore = 1 in { 173def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src), 174 "mov{w}\t{$src, $dst|$dst, $src}", []>; 175} 176def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src), 177 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 178def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src), 179 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 180def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src), 181 "mov{q}\t{$src, $dst|$dst, $src}", []>; 182let mayLoad = 1 in { 183def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src), 184 "mov{w}\t{$src, $dst|$dst, $src}", []>; 185} 186} // SchedRW 187 188//===----------------------------------------------------------------------===// 189// Segmentation support instructions. 190 191let SchedRW = [WriteSystem] in { 192def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB; 193 194let mayLoad = 1 in 195def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 196 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 197 OpSize16, NotMemoryFoldable; 198def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 199 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, 200 OpSize16, NotMemoryFoldable; 201 202// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo. 203let mayLoad = 1 in 204def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 205 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 206 OpSize32, NotMemoryFoldable; 207def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 208 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB, 209 OpSize32, NotMemoryFoldable; 210// i16mem operand in LAR64rm and GR32 operand in LAR64rr is not a typo. 211let mayLoad = 1 in 212def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 213 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 214def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 215 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 216 217// i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. 218let mayLoad = 1 in 219def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 220 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 221 OpSize16, NotMemoryFoldable; 222def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 223 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, 224 OpSize16, NotMemoryFoldable; 225// i16mem operand in LSL64rm and GR32 operand in LSL64rr is not a typo. 226let mayLoad = 1 in 227def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), 228 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 229 OpSize32, NotMemoryFoldable; 230def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 231 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB, 232 OpSize32, NotMemoryFoldable; 233let mayLoad = 1 in 234def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), 235 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 236def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), 237 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; 238 239def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; 240 241def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins), 242 "str{w}\t$dst", []>, TB, OpSize16; 243def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins), 244 "str{l}\t$dst", []>, TB, OpSize32; 245def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins), 246 "str{q}\t$dst", []>, TB; 247let mayStore = 1 in 248def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB; 249 250def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 251let mayLoad = 1 in 252def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB, NotMemoryFoldable; 253 254def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>, 255 OpSize16, Requires<[Not64BitMode]>; 256def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>, 257 OpSize32, Requires<[Not64BitMode]>; 258def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>, 259 OpSize16, Requires<[Not64BitMode]>; 260def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>, 261 OpSize32, Requires<[Not64BitMode]>; 262def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>, 263 OpSize16, Requires<[Not64BitMode]>; 264def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>, 265 OpSize32, Requires<[Not64BitMode]>; 266def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>, 267 OpSize16, Requires<[Not64BitMode]>; 268def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>, 269 OpSize32, Requires<[Not64BitMode]>; 270def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>, 271 OpSize16, TB; 272def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB, 273 OpSize32, Requires<[Not64BitMode]>; 274def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>, 275 OpSize16, TB; 276def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB, 277 OpSize32, Requires<[Not64BitMode]>; 278def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB, 279 OpSize32, Requires<[In64BitMode]>; 280def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB, 281 OpSize32, Requires<[In64BitMode]>; 282 283// No "pop cs" instruction. 284def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>, 285 OpSize16, Requires<[Not64BitMode]>; 286def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>, 287 OpSize32, Requires<[Not64BitMode]>; 288 289def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>, 290 OpSize16, Requires<[Not64BitMode]>; 291def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>, 292 OpSize32, Requires<[Not64BitMode]>; 293 294def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>, 295 OpSize16, Requires<[Not64BitMode]>; 296def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>, 297 OpSize32, Requires<[Not64BitMode]>; 298 299def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>, 300 OpSize16, TB; 301def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB, 302 OpSize32, Requires<[Not64BitMode]>; 303def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB, 304 OpSize32, Requires<[In64BitMode]>; 305 306def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>, 307 OpSize16, TB; 308def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB, 309 OpSize32, Requires<[Not64BitMode]>; 310def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB, 311 OpSize32, Requires<[In64BitMode]>; 312 313def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 314 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 315 Requires<[Not64BitMode]>; 316def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 317 "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 318 Requires<[Not64BitMode]>; 319 320def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 321 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 322def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 323 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 324def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 325 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB; 326 327def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 328 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 329 Requires<[Not64BitMode]>; 330def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 331 "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 332 Requires<[Not64BitMode]>; 333 334def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 335 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 336def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 337 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 338def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 339 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB; 340 341def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src), 342 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16; 343def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src), 344 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32; 345 346def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src), 347 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB; 348 349def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 350def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 351let mayLoad = 1 in { 352def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB, NotMemoryFoldable; 353def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable; 354} 355} // SchedRW 356 357//===----------------------------------------------------------------------===// 358// Descriptor-table support instructions 359 360let SchedRW = [WriteSystem] in { 361def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 362 "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 363def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 364 "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 365def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst), 366 "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 367def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 368 "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>; 369def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 370 "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>; 371def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst), 372 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>; 373def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins), 374 "sldt{w}\t$dst", []>, TB, OpSize16; 375let mayStore = 1 in 376def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst), 377 "sldt{w}\t$dst", []>, TB; 378def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), 379 "sldt{l}\t$dst", []>, OpSize32, TB; 380 381// LLDT is not interpreted specially in 64-bit mode because there is no sign 382// extension. 383def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), 384 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; 385 386def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 387 "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 388def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 389 "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 390def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src), 391 "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 392def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 393 "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; 394def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 395 "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>; 396def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src), 397 "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>; 398def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src), 399 "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 400let mayLoad = 1 in 401def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src), 402 "lldt{w}\t$src", []>, TB, NotMemoryFoldable; 403} // SchedRW 404 405//===----------------------------------------------------------------------===// 406// Specialized register support 407let SchedRW = [WriteSystem] in { 408let Uses = [EAX, ECX, EDX] in 409def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB; 410let Defs = [EAX, EDX], Uses = [ECX] in 411def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB; 412 413let Defs = [RAX, RDX], Uses = [ECX] in 414 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)]>, TB; 415 416def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins), 417 "smsw{w}\t$dst", []>, OpSize16, TB; 418def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins), 419 "smsw{l}\t$dst", []>, OpSize32, TB; 420// no m form encodable; use SMSW16m 421def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins), 422 "smsw{q}\t$dst", []>, TB; 423 424// For memory operands, there is only a 16-bit form 425def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst), 426 "smsw{w}\t$dst", []>, TB; 427 428def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src), 429 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 430let mayLoad = 1 in 431def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src), 432 "lmsw{w}\t$src", []>, TB, NotMemoryFoldable; 433 434let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 435 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB; 436} // SchedRW 437 438//===----------------------------------------------------------------------===// 439// Cache instructions 440let SchedRW = [WriteSystem] in { 441def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB; 442def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB; 443 444// wbnoinvd is like wbinvd, except without invalidation 445// encoding: like wbinvd + an 0xF3 prefix 446def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd", 447 [(int_x86_wbnoinvd)]>, XS, 448 Requires<[HasWBNOINVD]>; 449} // SchedRW 450 451//===----------------------------------------------------------------------===// 452// CET instructions 453// Use with caution, availability is not predicated on features. 454let SchedRW = [WriteSystem] in { 455 let Uses = [SSP] in { 456 let Defs = [SSP] in { 457 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src", 458 [(int_x86_incsspd GR32:$src)]>, XS; 459 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src", 460 [(int_x86_incsspq GR64:$src)]>, XS; 461 } // Defs SSP 462 463 let Constraints = "$src = $dst" in { 464 def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src), 465 "rdsspd\t$dst", 466 [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, XS; 467 def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src), 468 "rdsspq\t$dst", 469 [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, XS; 470 } 471 472 let Defs = [SSP] in { 473 def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp", 474 [(int_x86_saveprevssp)]>, XS; 475 def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src), 476 "rstorssp\t$src", 477 [(int_x86_rstorssp addr:$src)]>, XS; 478 } // Defs SSP 479 } // Uses SSP 480 481 def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 482 "wrssd\t{$src, $dst|$dst, $src}", 483 [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8PS; 484 def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 485 "wrssq\t{$src, $dst|$dst, $src}", 486 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8PS; 487 def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 488 "wrussd\t{$src, $dst|$dst, $src}", 489 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8PD; 490 def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 491 "wrussq\t{$src, $dst|$dst, $src}", 492 [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8PD; 493 494 let Defs = [SSP] in { 495 let Uses = [SSP] in { 496 def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy", 497 [(int_x86_setssbsy)]>, XS; 498 } // Uses SSP 499 500 def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src), 501 "clrssbsy\t$src", 502 [(int_x86_clrssbsy addr:$src)]>, XS; 503 } // Defs SSP 504} // SchedRW 505 506let SchedRW = [WriteSystem] in { 507 def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS; 508 def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS; 509} // SchedRW 510 511//===----------------------------------------------------------------------===// 512// XSAVE instructions 513let SchedRW = [WriteSystem] in { 514let Predicates = [HasXSAVE] in { 515let Defs = [EDX, EAX], Uses = [ECX] in 516 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB; 517 518let Uses = [EDX, EAX, ECX] in 519 def XSETBV : I<0x01, MRM_D1, (outs), (ins), 520 "xsetbv", 521 [(int_x86_xsetbv ECX, EDX, EAX)]>, TB; 522 523} // HasXSAVE 524 525let Uses = [EDX, EAX] in { 526def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 527 "xsave\t$dst", 528 [(int_x86_xsave addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 529def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst), 530 "xsave64\t$dst", 531 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 532def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 533 "xrstor\t$dst", 534 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE]>; 535def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst), 536 "xrstor64\t$dst", 537 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVE, In64BitMode]>; 538def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 539 "xsaveopt\t$dst", 540 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT]>; 541def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst), 542 "xsaveopt64\t$dst", 543 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, PS, Requires<[HasXSAVEOPT, In64BitMode]>; 544def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 545 "xsavec\t$dst", 546 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>; 547def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst), 548 "xsavec64\t$dst", 549 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>; 550def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 551 "xsaves\t$dst", 552 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 553def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst), 554 "xsaves64\t$dst", 555 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>; 556def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 557 "xrstors\t$dst", 558 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>; 559def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst), 560 "xrstors64\t$dst", 561 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>; 562} // Uses 563} // SchedRW 564 565//===----------------------------------------------------------------------===// 566// VIA PadLock crypto instructions 567let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in 568 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB; 569 570def : InstAlias<"xstorerng", (XSTORE)>; 571 572let SchedRW = [WriteSystem] in { 573let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 574 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB; 575 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB; 576 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB; 577 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB; 578 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB; 579} 580 581let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in { 582 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB; 583 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB; 584} 585let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 586 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB; 587} // SchedRW 588 589//==-----------------------------------------------------------------------===// 590// PKU - enable protection key 591let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 592 def WRPKRU : PseudoI<(outs), (ins GR32:$src), 593 [(int_x86_wrpkru GR32:$src)]>; 594 def RDPKRU : PseudoI<(outs GR32:$dst), (ins), 595 [(set GR32:$dst, (int_x86_rdpkru))]>; 596} 597 598let SchedRW = [WriteSystem] in { 599let Defs = [EAX, EDX], Uses = [ECX] in 600 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB; 601let Uses = [EAX, ECX, EDX] in 602 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB; 603} // SchedRW 604 605//===----------------------------------------------------------------------===// 606// FS/GS Base Instructions 607let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in { 608 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), 609 "rdfsbase{l}\t$dst", 610 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; 611 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), 612 "rdfsbase{q}\t$dst", 613 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; 614 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), 615 "rdgsbase{l}\t$dst", 616 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; 617 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), 618 "rdgsbase{q}\t$dst", 619 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; 620 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), 621 "wrfsbase{l}\t$src", 622 [(int_x86_wrfsbase_32 GR32:$src)]>, XS; 623 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), 624 "wrfsbase{q}\t$src", 625 [(int_x86_wrfsbase_64 GR64:$src)]>, XS; 626 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), 627 "wrgsbase{l}\t$src", 628 [(int_x86_wrgsbase_32 GR32:$src)]>, XS; 629 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), 630 "wrgsbase{q}\t$src", 631 [(int_x86_wrgsbase_64 GR64:$src)]>, XS; 632} 633 634//===----------------------------------------------------------------------===// 635// INVPCID Instruction 636let SchedRW = [WriteSystem] in { 637def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), 638 "invpcid\t{$src2, $src1|$src1, $src2}", 639 [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8PD, 640 Requires<[Not64BitMode, HasINVPCID]>; 641def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), 642 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD, 643 Requires<[In64BitMode, HasINVPCID]>; 644} // SchedRW 645 646let Predicates = [In64BitMode, HasINVPCID] in { 647 // The instruction can only use a 64 bit register as the register argument 648 // in 64 bit mode, while the intrinsic only accepts a 32 bit argument 649 // corresponding to it. 650 // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID 651 // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. 652 def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), 653 (INVPCID64 654 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), 655 addr:$src2)>; 656} 657 658 659//===----------------------------------------------------------------------===// 660// SMAP Instruction 661let Defs = [EFLAGS], SchedRW = [WriteSystem] in { 662 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB; 663 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB; 664} 665 666//===----------------------------------------------------------------------===// 667// SMX Instruction 668let SchedRW = [WriteSystem] in { 669let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in { 670 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB; 671} // Uses, Defs 672} // SchedRW 673 674//===----------------------------------------------------------------------===// 675// TS flag control instruction. 676let SchedRW = [WriteSystem] in { 677def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; 678} 679 680//===----------------------------------------------------------------------===// 681// IF (inside EFLAGS) management instructions. 682let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in { 683def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; 684def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; 685} 686 687//===----------------------------------------------------------------------===// 688// RDPID Instruction 689let SchedRW = [WriteSystem] in { 690def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 691 "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, XS, 692 Requires<[Not64BitMode, HasRDPID]>; 693def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, 694 Requires<[In64BitMode, HasRDPID]>; 695} // SchedRW 696 697let Predicates = [In64BitMode, HasRDPID] in { 698 // Due to silly instruction definition, we have to compensate for the 699 // instruction outputing a 64-bit register. 700 def : Pat<(int_x86_rdpid), 701 (EXTRACT_SUBREG (RDPID64), sub_32bit)>; 702} 703 704 705//===----------------------------------------------------------------------===// 706// PTWRITE Instruction - Write Data to a Processor Trace Packet 707let SchedRW = [WriteSystem] in { 708def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst), 709 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, XS, 710 Requires<[HasPTWRITE]>; 711def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst), 712 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, XS, 713 Requires<[In64BitMode, HasPTWRITE]>; 714 715def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst), 716 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, XS, 717 Requires<[HasPTWRITE]>; 718def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst), 719 "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, XS, 720 Requires<[In64BitMode, HasPTWRITE]>; 721} // SchedRW 722 723//===----------------------------------------------------------------------===// 724// Platform Configuration instruction 725 726// From ISA docs: 727// "This instruction is used to execute functions for configuring platform 728// features. 729// EAX: Leaf function to be invoked. 730// RBX/RCX/RDX: Leaf-specific purpose." 731// "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF, 732// AF, OF, and SF are cleared. In case of failure, the failure reason is 733// indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared." 734// Thus all these mentioned registers are considered clobbered. 735 736let SchedRW = [WriteSystem] in { 737let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in 738 def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB, 739 Requires<[HasPCONFIG]>; 740} // SchedRW 741