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Searched refs:PSTATE_ID_SOC_POWERDN (Results 1 – 9 of 9) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c67 case PSTATE_ID_SOC_POWERDN: in tegra_soc_validate_power_state()
175 (target == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
178 target = PSTATE_ID_SOC_POWERDN; in tegra_soc_get_target_pwr_state()
199 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_suspend()
202 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); in tegra_soc_pwr_domain_suspend()
204 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); in tegra_soc_pwr_domain_suspend()
346 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_power_down_wfi()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_psci_handlers.c154 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_suspend()
283 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
284 target = PSTATE_ID_SOC_POWERDN; in tegra_soc_get_target_pwr_state()
306 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_power_down_wfi()
384 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c112 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_suspend()
255 (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
256 target = PSTATE_ID_SOC_POWERDN; in tegra_soc_get_target_pwr_state()
277 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_power_down_wfi()
353 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { in tegra_soc_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t132/
Dtegra_def.h16 #define PSTATE_ID_SOC_POWERDN U(0xD) macro
25 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h17 #define PSTATE_ID_SOC_POWERDN U(27) macro
23 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
32 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_pm.c131 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; in tegra_get_sys_suspend_power_state()
212 PSTATE_ID_SOC_POWERDN) { in tegra_pwr_domain_suspend()
253 PSTATE_ID_SOC_POWERDN) { in tegra_pwr_domain_on_finish()
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/
Dplat_psci_handlers.c49 if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) { in tegra_soc_validate_power_state()
60 PSTATE_ID_SOC_POWERDN; in tegra_soc_validate_power_state()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_def.h49 #define PSTATE_ID_SOC_POWERDN U(2) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t194/
Dtegra_def.h25 #define PSTATE_ID_SOC_POWERDN U(2) macro