1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 14 * call as the `state-id` field in the 'power state' parameter. 15 ******************************************************************************/ 16 #define PSTATE_ID_SOC_POWERDN U(0xD) 17 18 /******************************************************************************* 19 * Platform power states (used by PSCI framework) 20 * 21 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 22 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 23 ******************************************************************************/ 24 #define PLAT_MAX_RET_STATE U(1) 25 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 26 27 /******************************************************************************* 28 * Chip specific page table and MMU setup constants 29 ******************************************************************************/ 30 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 31 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 32 33 /******************************************************************************* 34 * GIC memory map 35 ******************************************************************************/ 36 #define TEGRA_GICD_BASE U(0x50041000) 37 #define TEGRA_GICC_BASE U(0x50042000) 38 39 /******************************************************************************* 40 * Tegra micro-seconds timer constants 41 ******************************************************************************/ 42 #define TEGRA_TMRUS_BASE U(0x60005010) 43 #define TEGRA_TMRUS_SIZE U(0x1000) 44 45 /******************************************************************************* 46 * Tegra Clock and Reset Controller constants 47 ******************************************************************************/ 48 #define TEGRA_CAR_RESET_BASE U(0x60006000) 49 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 50 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 51 #define GPU_RESET_BIT (U(1) << 24) 52 #define GPU_SET_BIT (U(1) << 24) 53 54 /******************************************************************************* 55 * Tegra Flow Controller constants 56 ******************************************************************************/ 57 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 58 59 /******************************************************************************* 60 * Tegra Secure Boot Controller constants 61 ******************************************************************************/ 62 #define TEGRA_SB_BASE U(0x6000C200) 63 64 /******************************************************************************* 65 * Tegra Exception Vectors constants 66 ******************************************************************************/ 67 #define TEGRA_EVP_BASE U(0x6000F000) 68 69 /******************************************************************************* 70 * Tegra Miscellaneous register constants 71 ******************************************************************************/ 72 #define TEGRA_MISC_BASE U(0x70000000) 73 #define HARDWARE_REVISION_OFFSET U(0x804) 74 75 /******************************************************************************* 76 * Tegra UART controller base addresses 77 ******************************************************************************/ 78 #define TEGRA_UARTA_BASE U(0x70006000) 79 #define TEGRA_UARTB_BASE U(0x70006040) 80 #define TEGRA_UARTC_BASE U(0x70006200) 81 #define TEGRA_UARTD_BASE U(0x70006300) 82 #define TEGRA_UARTE_BASE U(0x70006400) 83 84 /******************************************************************************* 85 * Tegra Power Mgmt Controller constants 86 ******************************************************************************/ 87 #define TEGRA_PMC_BASE U(0x7000E400) 88 89 /******************************************************************************* 90 * Tegra Memory Controller constants 91 ******************************************************************************/ 92 #define TEGRA_MC_BASE U(0x70019000) 93 94 /* Memory Controller Interrupt Status */ 95 #define MC_INTSTATUS 0x00U 96 97 /* TZDRAM carveout configuration registers */ 98 #define MC_SECURITY_CFG0_0 U(0x70) 99 #define MC_SECURITY_CFG1_0 U(0x74) 100 #define MC_SECURITY_CFG3_0 U(0x9BC) 101 102 /* Video Memory carveout configuration registers */ 103 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 104 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 105 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 106 107 /******************************************************************************* 108 * Tegra TZRAM constants 109 ******************************************************************************/ 110 #define TEGRA_TZRAM_BASE U(0x7C010000) 111 #define TEGRA_TZRAM_SIZE U(0x10000) 112 113 #endif /* TEGRA_DEF_H */ 114