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Searched refs:RR (Results 1 – 25 of 365) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp98 RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { in normalize()
99 return RR; in normalize()
163 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM() argument
164 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
166 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
170 if (RR.Mask == LaneBitmask::getAll()) in aliasRM()
172 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
173 if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask) in aliasRM()
181 LaneBitmask M = RR.Mask; in aliasRM()
182 for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) { in aliasRM()
[all …]
DRDFRegisters.h84 bool operator== (const RegisterRef &RR) const {
85 return Reg == RR.Reg && Mask == RR.Mask;
88 bool operator!= (const RegisterRef &RR) const {
89 return !operator==(RR);
92 bool operator< (const RegisterRef &RR) const {
93 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
114 RegisterRef normalize(RegisterRef RR) const;
132 RegisterRef mapTo(RegisterRef RR, unsigned R) const;
154 bool aliasRM(RegisterRef RR, RegisterRef RM) const;
164 bool hasAliasOf(RegisterRef RR) const;
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DHexagonExpandCondsets.cpp182 bool operator== (RegisterRef RR) const { in operator ==()
183 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
185 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=()
186 bool operator< (RegisterRef RR) const { in operator <()
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
235 bool isIntReg(RegisterRef RR, unsigned &BW);
294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap() argument
296 unsigned Mask = getMaskForSub(RR.Sub) | Exec; in addRefToMap()
297 ReferenceMap::iterator F = Map.find(RR.Reg); in addRefToMap()
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DRDFGraph.cpp437 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { in setRegRef() argument
440 Ref.PR = G.pack(RR); in setRegRef()
833 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { in newPhiUse() argument
836 PUA.Addr->setRegRef(RR, *this); in newPhiUse()
849 RegisterRef RR, uint16_t Flags) { in newDef() argument
852 DA.Addr->setRegRef(RR, *this); in newDef()
926 RegisterRef RR = *I; in build() local
929 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); in build()
951 for (RegisterRef RR : EHRegs) { in build() local
955 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); in build()
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DBitTracker.cpp330 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
339 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) { in getRegBitWidth()
340 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); in getRegBitWidth()
343 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg)); in getRegBitWidth()
344 unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
348 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell() argument
350 uint16_t BW = getRegBitWidth(RR); in getCell()
354 if (TargetRegisterInfo::isPhysicalRegister(RR.Reg)) in getCell()
357 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); in getCell()
360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg); in getCell()
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DRDFCopy.cpp122 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { in run() argument
124 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
125 if ((RC.LaneMask & RR.Mask) == RC.LaneMask) in run()
126 return RR.Reg; in run()
127 for (MCSubRegIndexIterator S(RR.Reg, &TRI); S.isValid(); ++S) in run()
128 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Df.cpp62 boost::math::ntl::RR exp2(const boost::math::ntl::RR& x) in exp2()
67 boost::math::ntl::RR log2(const boost::math::ntl::RR& x) in log2()
72 boost::math::ntl::RR f(const boost::math::ntl::RR& x, int variant) in f()
88 const boost::math::tools::polynomial<boost::math::ntl::RR>& n, in show_extra()
89 const boost::math::tools::polynomial<boost::math::ntl::RR>& d, in show_extra()
90 const boost::math::ntl::RR& x_offset, in show_extra()
91 const boost::math::ntl::RR& y_offset, in show_extra()
/external/llvm/lib/Target/Hexagon/
DHexagonRDF.cpp37 bool HexagonRegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) in covers()
39 if (RRs.count(RR)) in covers()
42 if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) { in covers()
43 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); in covers()
45 bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg}); in covers()
46 bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg}); in covers()
51 if (RR.Sub == 0) { in covers()
53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); in covers()
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg); in covers()
59 return RegisterAliasInfo::covers(RRs, RR); in covers()
DRDFGraph.cpp382 return Ref.RR; in getRegRef()
389 void RefNode::setRegRef(RegisterRef RR) { in setRegRef() argument
392 Ref.RR = RR; in setRegRef()
593 bool RegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) const { in covers()
594 if (RRs.count(RR)) in covers()
601 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) { in covers()
602 if (RR.Sub != 0) in covers()
603 return RRs.count({RR.Reg, 0}); in covers()
608 unsigned Reg = RR.Sub == 0 ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub); in covers()
617 std::vector<RegisterRef> RegisterAliasInfo::getAliasSet(RegisterRef RR) const { in getAliasSet()
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DHexagonExpandCondsets.cpp219 bool operator== (RegisterRef RR) const { in operator ==()
220 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
222 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=()
223 bool operator< (RegisterRef RR) const { in operator <()
224 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
236 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
272 bool isIntReg(RegisterRef RR, unsigned &BW);
323 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap() argument
325 unsigned Mask = getMaskForSub(RR.Sub) | Exec; in addRefToMap()
326 ReferenceMap::iterator F = Map.find(RR.Reg); in addRefToMap()
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DRDFGraph.h374 RegisterRef(const RegisterRef &RR) = default;
375 RegisterRef &operator= (const RegisterRef &RR) = default;
376 bool operator== (const RegisterRef &RR) const {
377 return Reg == RR.Reg && Sub == RR.Sub;
379 bool operator!= (const RegisterRef &RR) const {
380 return !operator==(RR);
382 bool operator< (const RegisterRef &RR) const {
383 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
392 virtual std::vector<RegisterRef> getAliasSet(RegisterRef RR) const;
395 virtual bool covers(const RegisterSet &RRs, RegisterRef RR) const;
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DBitTracker.cpp314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
324 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) { in getRegBitWidth()
325 const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg); in getRegBitWidth()
329 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg)); in getRegBitWidth()
330 PhysR = RR.Reg; in getRegBitWidth()
333 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub); in getRegBitWidth()
340 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell() argument
342 uint16_t BW = getRegBitWidth(RR); in getCell()
346 if (TargetRegisterInfo::isPhysicalRegister(RR.Reg)) in getCell()
349 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); in getCell()
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DRDFLiveness.cpp111 RegisterRef RR = TA.Addr->getRegRef(); in getAllReachingDefs() local
112 if (RAI.covers(RR, RefRR)) { in getAllReachingDefs()
515 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(); in computePhiInfo() local
516 dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>'; in computePhiInfo()
604 RegisterRef RR = R.first; in computeLiveIns() local
605 if (!isRestricted(PA, UA, RR)) in computeLiveIns()
606 RR = getRestrictedRegRef(UA); in computeLiveIns()
610 if (!RAI.alias(R.first, RR)) in computeLiveIns()
612 for (auto D : getAllReachingDefs(RR, UA)) in computeLiveIns()
613 LOX[RR].insert(D.Id); in computeLiveIns()
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/external/mdnsresponder/mDNSCore/
DDNSCommon.h172 #define GetRRDomainNameTarget(RR) ( … argument
173 …((RR)->rrtype == kDNSType_NS || (RR)->rrtype == kDNSType_CNAME || (RR)->rrtype == kDNSType_PTR || …
174 …((RR)->rrtype == kDNSType_MX || (RR)->rrtype == kDNSType_AFSDB || (RR)->rrtype == kDNSType_RT || …
175 …((RR)->rrtype == kDNSType_SRV ) ? &(RR)->rdata->u.srv.target : mD…
203 #define PutResourceRecord(MSG, P, C, RR) PutResourceRecordTTL((MSG), (P), (C), (RR), (RR)->rrorigin… argument
210 #define PutRR_OS(P, C, RR) PutRR_OS_TTL((P), (C), (RR), (RR)->rroriginalttl) argument
265 #pragma mark - RR List Management & Task Management
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DScheduler.cpp85 void ResourceManager::use(ResourceRef RR) { in use() argument
87 ResourceState &RS = *Resources[RR.first]; in use()
88 RS.markSubResourceAsUsed(RR.second); in use()
97 if (!Current.isAResourceGroup() || Current.getResourceMask() == RR.first) in use()
100 if (Current.containsResource(RR.first)) { in use()
101 Current.markSubResourceAsUsed(RR.first); in use()
102 Current.removeFromNextInSequence(RR.first); in use()
107 void ResourceManager::release(ResourceRef RR) { in release() argument
108 ResourceState &RS = *Resources[RR.first]; in release()
110 RS.releaseSubResource(RR.second); in release()
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DExecuteStage.cpp33 for (const ResourceRef &RR : ResourcesFreed) in reclaimSchedulerResources() local
34 notifyResourceAvailable(RR); in reclaimSchedulerResources()
168 void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) { in notifyResourceAvailable() argument
169 LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.' in notifyResourceAvailable()
170 << RR.second << "]\n"); in notifyResourceAvailable()
172 Listener->onResourceAvailable(RR); in notifyResourceAvailable()
/external/vboot_reference/host/lib/
Dutil_misc.c39 BIGNUM *N0inv = NULL, *R = NULL, *RR = NULL; in vb_keyb_from_rsa() local
70 NEW_BIGNUM(RR); in vb_keyb_from_rsa()
98 BN_copy(RR, R); in vb_keyb_from_rsa()
99 BN_mul(RRTemp, RR, R, bn_ctx); in vb_keyb_from_rsa()
100 BN_mod(RR, RRTemp, N, bn_ctx); in vb_keyb_from_rsa()
118 BN_mod(rr, RR, B, bn_ctx); /* rr = RR mod B */ in vb_keyb_from_rsa()
122 BN_rshift(RR, RR, 32); /* RR = RR/B */ in vb_keyb_from_rsa()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/atomics/
Dload8.ll8 ; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
33 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
35 ; CHECK-NEXT: st [[RR]], [[RD]]
45 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
47 ; CHECK-NEXT: st [[RR]], [[RD]]
57 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
59 ; CHECK-NEXT: st [[RR]], [[RD]]
69 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
71 ; CHECK-NEXT: st [[RR]], [[RD]]
81 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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Dstore.ll6 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
16 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
17 ; CHECK-NEXT: std [[RD]]+1, [[RR:r[0-9]+]]
/external/openssh/
DREADME.dns10 (1) Server: Generate and publish the DNS RR
12 To create a DNS resource record (RR) containing a fingerprint of the
19 you should generate one RR for each key.
22 generic DNS RR format parsable by most modern name server
23 implementations. If your nameserver has support for the SSHFP RR
24 you can omit the -g flag and ssh-keygen will print a standard SSHFP RR.
26 To publish the fingerprint using the DNS you must add the generated RR
38 Upon connection the client will try to look up the fingerprint RR
/external/boringssl/src/crypto/fipsmodule/bn/
Dmontgomery.c133 BN_init(&ret->RR); in BN_MONT_CTX_new()
144 BN_free(&mont->RR); in BN_MONT_CTX_free()
154 if (!BN_copy(&to->RR, &from->RR) || in BN_MONT_CTX_copy()
228 BN_zero(&mont->RR); in BN_MONT_CTX_set()
229 int ok = BN_set_bit(&mont->RR, lgBigR * 2) && in BN_MONT_CTX_set()
230 BN_mod(&mont->RR, &mont->RR, &mont->N, ctx) && in BN_MONT_CTX_set()
231 bn_resize_words(&mont->RR, mont->N.width); in BN_MONT_CTX_set()
253 if (!bn_mod_exp_base_2_consttime(&mont->RR, lgBigR * 2, &mont->N, ctx) || in BN_MONT_CTX_new_consttime()
254 !bn_resize_words(&mont->RR, mont->N.width)) { in BN_MONT_CTX_new_consttime()
285 return BN_mod_mul_montgomery(ret, a, &mont->RR, mont, ctx); in BN_to_montgomery()
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/external/vboot_reference/utility/
DdumpRSAPublicKey.c46 BIGNUM *N0inv= NULL, *R = NULL, *RR = NULL, *RRTemp = NULL, *NnumBits = NULL; in output() local
65 RR = BN_new(); in output()
92 BN_copy(RR, R); in output()
93 BN_mul(RRTemp, RR, R, bn_ctx); in output()
94 BN_mod(RR, RRTemp, N, bn_ctx); in output()
113 BN_mod(rr, RR, B, bn_ctx); /* rr = RR mod B */ in output()
118 BN_rshift(RR, RR, 32); /* RR = RR/B */ in output()
/external/clang/test/PCH/
Dcxx-reference.h4 typedef char (&&RR);
12 RR &lrrr = c;
13 RR &&rrrr = 'c';
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-xray/
Dxray-account.cpp310 auto &RR = std::get<2>(R); in exportStats() local
314 return LR.Count < RR.Count; in exportStats()
316 return LR.Count > RR.Count; in exportStats()
320 return LR.Min < RR.Min; in exportStats()
322 return LR.Min > RR.Min; in exportStats()
326 return LR.Median < RR.Median; in exportStats()
328 return LR.Median > RR.Median; in exportStats()
332 return LR.Pct90 < RR.Pct90; in exportStats()
334 return LR.Pct90 > RR.Pct90; in exportStats()
338 return LR.Pct99 < RR.Pct99; in exportStats()
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/external/clang/lib/StaticAnalyzer/Checkers/
DPointerSubChecker.cpp48 const MemRegion *RR = RV.getAsRegion(); in checkPreStmt() local
50 if (!(LR && RR)) in checkPreStmt()
54 const MemRegion *BaseRR = RR->getBaseRegion(); in checkPreStmt()

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