| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | InfoByHwMode.cpp | 119 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
125 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
126 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
130 return RegSize <= I.RegSize && in isSubClassOf()
136 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
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| D | InfoByHwMode.h | 142 unsigned RegSize; member
150 return std::tie(RegSize, SpillSize, SpillAlignment) ==
151 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
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| D | RegisterInfoEmitter.cpp | 1038 uint32_t RegSize = 0; in runMCDesc() local
1040 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1045 << RegSize/8 << ", " in runMCDesc()
1247 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 128 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
129 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
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| D | MipsSEFrameLowering.cpp | 79 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
81 unsigned MFLoOpc, unsigned RegSize);
199 unsigned RegSize) { in expandLoadACC() argument
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
218 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
224 unsigned RegSize) { in expandStoreACC() argument
232 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
242 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 124 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
130 SmallBitVector Coverage(RegSize, false); in addMachineReg()
141 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
164 if (CurPos < RegSize) in addMachineReg()
165 DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"}); in addMachineReg()
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 222 unsigned RegSize = 0; in getInstrMappingImpl() local
272 RegSize = getSizeInBits(Reg, MRI, TRI); in getInstrMappingImpl()
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); in getInstrMappingImpl()
300 Mapping.setOperandMapping(OpIdx, RegSize, *RegBank); in getInstrMappingImpl()
372 unsigned RegSize = MRI.getSize(Reg); in getSizeInBits() local
375 if (RegSize) in getSizeInBits()
376 return RegSize; in getSizeInBits()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece() local
136 SmallBitVector Coverage(RegSize, false); in AddMachineRegPiece()
145 SmallBitVector Intersection(RegSize, false); in AddMachineRegPiece()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && in processLogicalImmediate()
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
221 unsigned Size = RegSize; in processLogicalImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 60 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62 unsigned MFLoOpc, unsigned RegSize);
179 unsigned RegSize) { in expandLoadACC() argument
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
198 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
204 unsigned RegSize) { in expandStoreACC() argument
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
222 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U))) in processLogicalImmediate()
220 unsigned Size = RegSize; in processLogicalImmediate()
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| /external/capstone/ |
| D | MCRegisterInfo.h | 39 uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 471 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
474 if (RegSize) in getRegSizeInBits()
475 return RegSize; in getRegSizeInBits()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
82 unsigned getSize() const { return RegSize; } in getSize()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 740 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} in LogicOp()
742 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
744 explicit operator bool() const { return RegSize; } in operator bool()
746 unsigned RegSize, ImmLSB, ImmSize; member
842 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
844 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
846 if (And.RegSize == 64) { in convertToThreeAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 225 unsigned RegSize, SpillSize, SpillAlignment; member
315 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 1001 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
1003 explicit operator bool() const { return RegSize; } in operator bool()
1005 unsigned RegSize = 0; member
1104 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
1106 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
1108 if (And.RegSize == 64) { in convertToThreeAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1670 unsigned RegSize; in emitLogicalOp_ri() local
1681 RegSize = 32; in emitLogicalOp_ri()
1687 RegSize = 64; in emitLogicalOp_ri()
1691 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1696 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4032 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4079 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4139 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4187 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4260 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1616 unsigned RegSize; in emitLogicalOp_ri() local
1627 RegSize = 32; in emitLogicalOp_ri()
1633 RegSize = 64; in emitLogicalOp_ri()
1637 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1642 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
3946 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
3993 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4053 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4101 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4174 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 146 int RegSize; in sizeOfSPAdjustment() local
149 RegSize = 8; in sizeOfSPAdjustment()
153 RegSize = 4; in sizeOfSPAdjustment()
166 count += RegSize; in sizeOfSPAdjustment()
|
| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 692 unsigned RegSize, in validateGlobalRegisterVariable() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 3215 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjLongJmp() local
3235 .addImm(RegSize); in emitEHSjLjLongJmp()
3242 .addImm(2 * RegSize); in emitEHSjLjLongJmp()
3248 .addImm(3 * RegSize); in emitEHSjLjLongJmp()
3269 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjSetJmp() local
3341 .addImm(RegSize) in emitEHSjLjSetJmp()
3348 .addImm(2 * RegSize) in emitEHSjLjSetJmp()
3354 .addImm(3 * RegSize) in emitEHSjLjSetJmp()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 3184 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjLongJmp() local
3204 .addImm(RegSize); in emitEHSjLjLongJmp()
3211 .addImm(2 * RegSize); in emitEHSjLjLongJmp()
3217 .addImm(3 * RegSize); in emitEHSjLjLongJmp()
3237 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjSetJmp() local
3308 .addImm(RegSize) in emitEHSjLjSetJmp()
3315 .addImm(2 * RegSize) in emitEHSjLjSetJmp()
3321 .addImm(3 * RegSize) in emitEHSjLjSetJmp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 191 int RegSize; in sizeOfSPAdjustment() local
194 RegSize = 8; in sizeOfSPAdjustment()
198 RegSize = 4; in sizeOfSPAdjustment()
211 count += RegSize; in sizeOfSPAdjustment()
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| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 3764 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
3766 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
3769 RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
4729 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity(); in EmitAAPCSVAArg() local
4738 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
4747 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
4788 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
|