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Searched refs:SPM_BASE (Results 1 – 8 of 8) sorted by relevance

/external/arm-trusted-firmware/plat/mediatek/mt6795/include/
Dspm.h10 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
11 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
12 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
13 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
14 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
15 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
16 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
17 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
18 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
19 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
[all …]
Dplatform_def.h24 #define SPM_BASE (IO_PHYS + 0x6000) macro
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm.h9 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
10 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
11 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
12 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
13 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
14 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
15 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
16 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
17 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
18 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm.h14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define PCM_IM_PTR (SPM_BASE + 0x020)
23 #define PCM_IM_LEN (SPM_BASE + 0x024)
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc_private.h23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
29 #define SPM_PWR_STATUS (SPM_BASE + 0x180)
30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
33 #define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dplat_dcm.c19 #define PWR_STATUS (SPM_BASE + 0x180)
/external/arm-trusted-firmware/plat/mediatek/mt8173/include/
Dmt8173_def.h22 #define SPM_BASE (IO_PHYS + 0x6000) macro
/external/arm-trusted-firmware/plat/mediatek/mt8183/include/
Dplatform_def.h19 #define SPM_BASE (IO_PHYS + 0x6000) macro