| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 46 SXTH, enumerator
65 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
132 case 5: return AArch64_AM::SXTH; in getExtendType()
159 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 57 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
58 // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 34 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 48 "Sxth", // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield-extract.ll | 84 ; SHR with multiple uses is fine as SXTH and SBFX are both aliases of SBFM.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | bitfield-extract.ll | 84 ; SHR with multiple uses is fine as SXTH and SBFX are both aliases of SBFM.
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 365 SXTH, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 82 COMPARE_MACRO(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); in TEST()
321 COMPARE(adds(w21, w22, Operand(w23, SXTH, 2)), "adds w21, w22, w23, sxth #2"); in TEST()
325 COMPARE(cmn(x2, Operand(x3, SXTH, 4)), "cmn x2, w3, sxth #4"); in TEST()
347 COMPARE(subs(w21, w22, Operand(w23, SXTH, 2)), "subs w21, w22, w23, sxth #2"); in TEST()
2374 COMPARE_MACRO(Csel(x3, x4, Operand(x5, SXTH), eq), in TEST()
2379 Operand(x5, SXTH), in TEST()
2394 COMPARE_MACRO(Csel(x9, Operand(x10, SXTH), x11, eq), in TEST()
2398 Operand(x10, SXTH), in TEST()
|
| D | test-api-aarch64.cc | 474 VIXL_CHECK(!Operand(w14, SXTH).IsPlainRegister()); in TEST()
|
| D | test-assembler-aarch64.cc | 191 __ Mvn(x13, Operand(x2, SXTH, 3)); in TEST()
365 __ Mov(x26, Operand(x13, SXTH, 3)); in TEST()
419 __ Mov(w22, Operand(w11, SXTH, 1)); in TEST()
426 __ Mov(x28, Operand(x12, SXTH, 1)); in TEST()
502 __ Orr(x11, x0, Operand(x1, SXTH, 1)); in TEST()
596 __ Orn(x11, x0, Operand(x1, SXTH, 1)); in TEST()
663 __ And(x11, x0, Operand(x1, SXTH, 1)); in TEST()
809 __ Bic(x11, x0, Operand(x1, SXTH, 1)); in TEST()
941 __ Eor(x11, x0, Operand(x1, SXTH, 1)); in TEST()
1008 __ Eon(x11, x0, Operand(x1, SXTH, 1)); in TEST()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 406 SXTH, enumerator
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 239 return Size == 8 ? ARM::SXTB : ARM::SXTH; in selectSimpleExtOpc()
|
| D | ARMFastISel.cpp | 2669 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2909 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
|
| D | ARMScheduleSwift.td | 162 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| D | ARMScheduleR52.td | 216 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 175 #define SXTH 0xb200 macro
768 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| D | sljitNativeARM_32.c | 132 #define SXTH 0xe6bf0070 macro
1067 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2643 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2883 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
|
| D | ARMScheduleSwift.td | 157 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
|