| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 46 ; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
47 ; O32-DAG: sw [[VA]], 0([[SP]])
49 ; N32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 8
50 ; N32-DAG: sw [[VA]], 0([[SP]])
52 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
53 ; N64-DAG: sd [[VA]], 0([[SP]])
55 ; Store [[VA]]
56 ; O32-DAG: sw [[VA]], 0([[SP]])
60 ; Increment [[VA]]
61 ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 46 ; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
47 ; O32-DAG: sw [[VA]], 0([[SP]])
49 ; N32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 8
50 ; N32-DAG: sw [[VA]], 0([[SP]])
52 ; N64-DAG: daddiu [[VA:\$[0-9]+]], [[SP]], 8
53 ; N64-DAG: sd [[VA]], 0([[SP]])
55 ; Store [[VA]]
56 ; O32-DAG: sw [[VA]], 0([[SP]])
60 ; Increment [[VA]]
61 ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_xxpermdi.ll | 68 define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
70 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1>
77 define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) {
79 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1>
86 define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) {
88 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0>
95 define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) {
97 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0>
104 define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) {
106 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3>
[all …]
|
| D | vec_sldwi.ll | 68 define <4 x i32> @check_le_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {
70 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
76 define <4 x i32> @check_le_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) {
78 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
85 define <4 x i32> @check_le_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) {
87 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
94 define <4 x i32> @check_le_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) {
96 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
103 define <4 x i32> @check_le_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) {
105 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2ISelLowering.cpp | 51 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
52 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
57 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
61 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
104 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
106 EVT ValVT = VA.getValVT(); in LowerFormalArguments()
109 if (VA.isRegLoc()) { in LowerFormalArguments()
110 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
111 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
122 if (VA.getLocInfo() != CCValAssign::Full) { in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 130 CCValAssign &VA = ArgLocs[j]; in handleAssignments() local
131 assert(VA.getValNo() == i && "Location doesn't correspond to current arg"); in handleAssignments()
133 if (VA.needsCustom()) { in handleAssignments()
138 if (VA.isRegLoc()) in handleAssignments()
139 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); in handleAssignments()
140 else if (VA.isMemLoc()) { in handleAssignments()
141 unsigned Size = VA.getValVT() == MVT::iPTR in handleAssignments()
143 : alignTo(VA.getValVT().getSizeInBits(), 8) / 8; in handleAssignments()
144 unsigned Offset = VA.getLocMemOffset(); in handleAssignments()
147 Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA); in handleAssignments()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 115 CCValAssign &VA) override { in assignValueToReg()
116 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
117 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
119 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size"); in assignValueToReg()
120 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
122 unsigned ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
128 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
132 unsigned ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
134 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
141 CCValAssign VA = VAs[0]; in assignCustomValue() local
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 776 CCValAssign VA = PendingLocs[0]; in CC_RISCV() local
780 return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT, in CC_RISCV()
865 const CCValAssign &VA, const SDLoc &DL) { in unpackFromRegLoc() argument
868 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
869 EVT ValVT = VA.getValVT(); in unpackFromRegLoc()
873 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
876 switch (VA.getLocInfo()) { in unpackFromRegLoc()
892 const CCValAssign &VA, const SDLoc &DL) { in unpackFromMemLoc() argument
895 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
896 EVT ValVT = VA.getValVT(); in unpackFromMemLoc()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 264 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
268 switch (VA.getLocInfo()) { in LowerCall()
274 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
277 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
280 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
286 if (VA.isRegLoc()) { in LowerCall()
287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
289 assert(VA.isMemLoc() && "Must be register or memory argument."); in LowerCall()
294 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall()
378 const CCValAssign &VA = RVLocs[i]; in lowerCallResult() local
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/XRay/ |
| D | GraphTest.cpp | 21 unsigned VA; member
67 std::vector<unsigned> VA({0u, 3u, 5u, 7u, 11u, 13u, 17u}); in graphVertexTester() local
75 EXPECT_EQ(VA[u], EVV->VA); in graphVertexTester()
84 EXPECT_EQ(VA[VVT.first], VVT.second.VA); in graphVertexTester()
93 std::vector<unsigned> VA({0u, 3u, 5u, 7u, 11u, 13u, 17u}); in graphEdgeTester() local
101 EXPECT_EQ(VA[u.first] * VA[u.second] * ((u.first > u.second) ? 2 : 1), in graphEdgeTester()
111 EXPECT_EQ(VA[EV.first.first] * VA[EV.first.second] * in graphEdgeTester()
204 EXPECT_EQ(1u, MG[0u].VA); in TEST()
207 EXPECT_EQ(1u, MG[0u].VA); in TEST()
210 EXPECT_EQ(1u, T->VA); in TEST()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepIICHVX.td | 97 InstrItinData <tc_0317c6ca, /*SLOT0,STORE,VA*/
172 InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/
190 InstrItinData <tc_5a9fc4ec, /*SLOT0123,VA*/
205 InstrItinData <tc_5cbf490b, /*SLOT01,LOAD,VA*/
211 InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
222 InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
245 InstrItinData <tc_71337255, /*SLOT0123,VA*/
287 InstrItinData <tc_85d237e3, /*SLOT0,STORE,VA*/
319 InstrItinData <tc_9777e6bf, /*SLOT0,VA*/
335 InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 234 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
235 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
239 if (VA.needsCustom()) { in LowerReturn_32()
240 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
251 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
254 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
258 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 232 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
237 if (VA.needsCustom()) { in LowerReturn_32()
238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
252 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 171 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
172 if (VA.isRegLoc()) { in LowerFormalArguments()
174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
183 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
189 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
191 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
192 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
194 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
196 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
197 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | madak.ll | 9 ; GFX6: buffer_load_dword [[VA:v[0-9]+]]
12 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]]
13 ; GCN: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
35 ; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
38 ; GFX8_9: {{flat|global}}_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}
42 ; GCN-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
43 ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VA]], [[VC]]
70 ; GCN: {{buffer|flat|global}}_load_dword [[VA:v[0-9]+]]
71 ; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
89 ; GFX6: buffer_load_dword [[VA:v[0-9]+]]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 225 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
226 if (VA.isRegLoc()) { in LowerFormalArguments()
228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
241 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
246 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
248 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
249 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
251 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
253 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
254 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 127 CCValAssign &VA) override { in assignValueToReg()
139 unsigned ValSize = VA.getValVT().getSizeInBits(); in assignValueToReg()
140 unsigned LocSize = VA.getLocVT().getSizeInBits(); in assignValueToReg()
146 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
152 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
153 unsigned ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
155 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
240 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
248 CCValAssign &VA) override { in assignValueToReg()
251 switch (VA.getLocInfo()) { in assignValueToReg()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 80 CCValAssign &VA = ArgLocs[i]; in lowerFormalArguments() local
82 assert(VA.isRegLoc() && "Not yet implemented"); in lowerFormalArguments()
84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
87 switch (VA.getLocInfo()) { in lowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Demangle/ |
| D | ms-return-qualifiers.test | 97 ?d3@@YA?AV?$B@VA@@@@XZ
100 ?d4@@YAPAV?$B@VA@@@@XZ
103 ?d5@@YAPBV?$B@VA@@@@XZ
106 ?d6@@YAPCV?$B@VA@@@@XZ
109 ?d7@@YAPDV?$B@VA@@@@XZ
112 ?d8@@YAAAV?$B@VA@@@@XZ
115 ?d9@@YAABV?$B@VA@@@@XZ
118 ?d10@@YAACV?$B@VA@@@@XZ
121 ?d11@@YAADV?$B@VA@@@@XZ
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-pdbdump/ |
| D | load-address.test | 4 ; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s
9 ; VA: ---EXTERNALS---
10 ; VA: [0x40001010] _main
|
| /external/llvm/test/tools/llvm-pdbdump/ |
| D | load-address.test | 4 ; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s
9 ; VA: ---EXTERNALS---
10 ; VA: [0x40001010] _main
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | madak.ll | 10 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
12 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
33 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr…
37 ; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VB]], [[VA]], [[VK]]
38 ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VC]], [[VA]]
65 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
66 ; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
84 ; GCN: buffer_load_dword [[VA:v[0-9]+]]
86 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0
106 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]]
[all …]
|
| /external/clang/test/Parser/ |
| D | cxx-using-declaration.cpp | 4 int VA; variable
9 using A::VA;
15 VA = 1; in main()
|
| /external/clang/test/CXX/special/class.dtor/ |
| D | p3-0x.cpp | 140 struct VA { struct
142 virtual ~VA() {} in ~VA() argument
145 struct VB : VA
149 struct TVB : VA
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 433 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
434 if (VA.isRegLoc()) { in LowerCCCArguments()
436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
454 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
456 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
457 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
459 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
461 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
462 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
[all …]
|