| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 55 VOPC = 1 << 10 variable in Format
836 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
842 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
844 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
846 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
848 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
852 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
854 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
856 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
858 opcode(name, gfx7, gfx9, gfx10, Format.VOPC, True, False)
[all …]
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| D | aco_validate.cpp | 116 else if ((uint32_t)base_format & (uint32_t)Format::VOPC) in validate_ir()
117 base_format = Format::VOPC; in validate_ir()
137 base_format == Format::VOPC || in validate_ir()
146 base_format == Format::VOPC, in validate_ir()
153 if (base_format == Format::VOPC) { in validate_ir()
242 instr->format == Format::VOPC || in validate_ir()
264 if ((int) instr->format & (int) Format::VOPC || in validate_ir()
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| D | aco_ir.cpp | 174 if (vop3->clamp && instr->format == asVOP3(Format::VOPC) && chip != GFX8) in can_use_SDWA()
207 if ((unsigned)instr->format & (unsigned)Format::VOPC) in can_use_SDWA()
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| D | aco_optimizer.cpp | 1093 if ((uint16_t) instr->format & (uint16_t) Format::VOPC) { in label_instruction()
1371 if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */ in label_instruction()
1695 …VOP3A_instruction *vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1… in combine_ordering_test()
1703 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_ordering_test()
1766 …_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_comparison_ordering()
1775 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_comparison_ordering()
1885 …_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1); in combine_constant_comparison_ordering()
1894 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1); in combine_constant_comparison_ordering()
1934 …truction *new_vop3 = create_instruction<VOP3A_instruction>(new_opcode, asVOP3(Format::VOPC), 2, 1); in combine_inverse_comparison()
1944 new_opcode, (Format)((uint16_t)Format::SDWA | (uint16_t)Format::VOPC), 2, 1); in combine_inverse_comparison()
[all …]
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| D | aco_ir.h | 101 VOPC = 1 << 10, enumerator
242 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()
920 || ((uint16_t) format & (uint16_t) Format::VOPC) == (uint16_t) Format::VOPC in isVALU()
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| D | aco_assembler.cpp | 278 case Format::VOPC: { in emit_instruction()
559 } else if ((uint16_t) instr->format & (uint16_t) Format::VOPC) { in emit_instruction()
659 if ((uint16_t)instr->format & (uint16_t)Format::VOPC) { in emit_instruction()
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| D | aco_insert_NOPs.cpp | 543 if ((uint32_t) instr->format & (uint32_t) Format::VOPC) in VALU_writes_sgpr()
636 if (instr->format == Format::VOPC) { in handle_instruction_gfx10()
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| D | aco_opt_value_numbering.cpp | 177 if ((uint32_t) a->format & (uint32_t) Format::VOPC && a->pass_flags != b->pass_flags) in operator ()()
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| D | README-ISA.md | 207 Any permlane instruction that follows any VOPC instruction.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstrFormats.td | 146 // Encoding used for VOPC instructions encoded as VOP3
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
286 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
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| D | SIInstrFormats.td | 34 field bits<1> VOPC = 0;
70 let TSFlags{13} = VOPC;
127 let VOPC = 1;
429 // Encoding used for VOPC instructions encoded as VOP3
430 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
653 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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| D | SIDefines.h | 31 VOPC = 1 << 13, enumerator
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| D | SIInstrInfo.h | 272 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
276 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrInfo.td | 1320 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1329 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1342 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1359 ""); // use $sdst for VOPC
1374 " vcc", // use vcc token as dst for VOPC instructioins
1391 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1558 // VOPC instructions are a special case because for the 32-bit
1624 // This class is used only with VOPC instructions. Use $sdst for out operand
2310 def _si : VOPC<op.SI, ins, asm, []>,
2322 def _vi : VOPC<op.VI, ins, asm, []>,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 41 field bit VOPC = 0;
136 let TSFlags{9} = VOPC;
191 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
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| D | VOPCInstructions.td | 32 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
49 // VOPC classes
52 // VOPC instructions are a special case because for the 32-bit
82 let VOPC = 1;
117 // This class is used only with VOPC instructions. Use $sdst for out operand
690 // Encoding used for VOPC instructions encoded as VOP3
691 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
928 // Encoding used for VOPC instructions encoded as VOP3
929 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
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| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstrInfo.td | 1100 SDWAVopcDst, // VOPC
1461 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1479 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1493 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1558 ""); // use $sdst for VOPC
1572 " vcc", // use vcc token as dst for VOPC instructioins
1589 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1601 "$sdst", // VOPC
1617 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
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| D | SIDefines.h | 35 VOPC = 1 << 9, enumerator
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| D | SIInstrInfo.h | 397 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
401 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| D | AMDGPU.td | 218 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
230 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 101 VOP1, VOP2, VOP3, VOPC Instructions
107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUOperandSyntax.rst | 648 VOP1/VOP2/VOPC SDWA Modifiers
740 VOP1/VOP2/VOPC SDWA Operand Modifiers
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2687 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC); in cvtSdwaVOPC()
2703 if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
2738 case SIInstrFlags::VOPC: { in cvtSDWA()
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