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Searched refs:W0 (Results 1 – 25 of 236) sorted by relevance

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/external/v8/src/codegen/x64/
Dfma-instr.h21 V(vfmadd132ss, LIG, 66, 0F, 38, W0, 99) \
22 V(vfmadd213ss, LIG, 66, 0F, 38, W0, a9) \
23 V(vfmadd231ss, LIG, 66, 0F, 38, W0, b9) \
24 V(vfmsub132ss, LIG, 66, 0F, 38, W0, 9b) \
25 V(vfmsub213ss, LIG, 66, 0F, 38, W0, ab) \
26 V(vfmsub231ss, LIG, 66, 0F, 38, W0, bb) \
27 V(vfnmadd132ss, LIG, 66, 0F, 38, W0, 9d) \
28 V(vfnmadd213ss, LIG, 66, 0F, 38, W0, ad) \
29 V(vfnmadd231ss, LIG, 66, 0F, 38, W0, bd) \
30 V(vfnmsub132ss, LIG, 66, 0F, 38, W0, 9f) \
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp307 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate() local
319 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
321 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
323 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
329 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate()
341 uint16_t RW = W0; in evaluate()
350 uint16_t RW = W0; in evaluate()
366 assert(W0 == 64 && W1 == 32); in evaluate()
367 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate()
375 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs); in evaluate()
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DHexagonVectorPrint.cpp76 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
187 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
DHexagonCallingConv.td90 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
104 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
122 CCAssignToReg<[W0]>>>,
130 CCAssignToReg<[W0]>>>,
/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp241 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate() local
253 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
255 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
257 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate()
275 uint16_t RW = W0; in evaluate()
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate()
285 W0 = 8; // XXX Pred size in evaluate()
286 return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs); in evaluate()
298 assert(W0 == 64 && W1 == 32); in evaluate()
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/external/libxaac/decoder/armv8/
Dixheaacd_calcmaxspectralline.s71 MOV W0, W4
72 CMP W0, #0
74 CNEG W0, W0, LE
75 CLZ W0, W0
76 SUB W0, W0, #1
/external/iptables/utils/
Dpf.os223 S4:64:1:60:M1360,S,T,N,W0: Linux:google::Linux (Google crawlbot)
225 S2:64:1:60:M*,S,T,N,W0: Linux:2.4::Linux 2.4 (big boy)
226 S3:64:1:60:M*,S,T,N,W0: Linux:2.4:.18-21:Linux 2.4.18 and newer
227 S4:64:1:60:M*,S,T,N,W0: Linux:2.4::Linux 2.4/2.6 <= 2.6.7
228 S4:64:1:60:M*,S,T,N,W0: Linux:2.6:.1-7:Linux 2.4/2.6 <= 2.6.7
242 S20:64:1:60:M*,S,T,N,W0: Linux:2.2:20-25:Linux 2.2.20 and newer
243 S22:64:1:60:M*,S,T,N,W0: Linux:2.2::Linux 2.2
244 S11:64:1:60:M*,S,T,N,W0: Linux:2.2::Linux 2.2
248 S4:64:1:48:M1460,N,W0: Linux:2.4:cluster:Linux 2.4 in cluster
253 T4:64:1:60:M1412,S,T,N,W0: Linux:2.4::Linux 2.4 (late, uncommon)
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/external/boringssl/src/crypto/fipsmodule/sha/asm/
Dsha512-armv8.pl343 my ($W0,$W1)=("v16.4s","v17.4s");
363 ld1.32 {$W0},[$Ktbl],#16
374 add.i32 $W0,$W0,@MSG[0]
377 sha256h $ABCD,$EFGH,$W0
378 sha256h2 $EFGH,$abcd,$W0
381 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
385 add.i32 $W0,$W0,@MSG[0]
387 sha256h $ABCD,$EFGH,$W0
388 sha256h2 $EFGH,$abcd,$W0
390 ld1.32 {$W0},[$Ktbl],#16
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Dsha256-armv4.pl606 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
631 vld1.32 {$W0},[$Ktbl]!
643 vadd.i32 $W0,$W0,@MSG[0]
646 sha256h $ABCD,$EFGH,$W0
647 sha256h2 $EFGH,$abcd,$W0
650 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
654 vadd.i32 $W0,$W0,@MSG[0]
656 sha256h $ABCD,$EFGH,$W0
657 sha256h2 $EFGH,$abcd,$W0
659 vld1.32 {$W0},[$Ktbl]!
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Dsha1-armv8.pl245 my ($W0,$W1)=("v20.4s","v21.4s");
270 add.i32 $W0,@Kxx[0],@MSG[0]
277 sha1c $ABCD,$E,$W0 // 0
278 add.i32 $W0,@Kxx[$j],@MSG[2]
292 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
301 sha1p $ABCD,$E0,$W0
Dsha1-armv4-large.pl617 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
650 vadd.i32 $W0,@Kxx[0],@MSG[0]
658 sha1c $ABCD,$E,$W0
659 vadd.i32 $W0,@Kxx[$j],@MSG[2]
673 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
682 sha1p $ABCD,$E0,$W0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll35 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
37 ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
38 ; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
42 ; ALL: st.w $w[[W0]], 0($[[R0]])
69 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
71 ; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
72 ; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
76 ; ALL: st.w $w[[W0]], 0($[[R0]])
99 ; ALL: move.v $w[[W0:13]], $w12
100 ; NOODDSPREG: move.v $w[[W0:12]], $w13
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/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll35 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
37 ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
38 ; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
42 ; ALL: st.w $w[[W0]], 0($[[R0]])
69 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
71 ; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
72 ; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
76 ; ALL: st.w $w[[W0]], 0($[[R0]])
99 ; ALL: move.v $w[[W0:13]], $w12
100 ; NOODDSPREG: move.v $w[[W0:12]], $w13
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Df16-llvm-ir.ll52 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
53 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
80 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
81 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
126 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
127 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
197 ; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
198 ; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
232 ; MIPS32: fill.w $w[[W0:[0-9]+]], $[[R0]]
234 ; MIPS32: insert.w $w[[W0]][1], $[[R1]]
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Dfexuprl.ll14 ; CHECK: ld.h $w[[W0:[0-9]+]], 0(${{[0-9]+}})
15 ; CHECK: fexupl.w $w[[W1:[0-9]+]], $w[[W0]]
21 ; CHECK: fexupr.w $w[[W2:[0-9]+]], $w[[W0]]
/external/llvm/test/CodeGen/AArch64/
Darm64-unaligned_ldst.ll21 ; CHECK: ldr [[W0:w[0-9]+]], [x1]
22 ; CHECK: str [[W0]], [x0]
34 ; CHECK: ldrh [[W0:w[0-9]+]], [x1]
35 ; CHECK: strh [[W0]], [x0]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-unaligned_ldst.ll21 ; CHECK: ldr [[W0:w[0-9]+]], [x1]
22 ; CHECK: str [[W0]], [x0]
34 ; CHECK: ldrh [[W0:w[0-9]+]], [x1]
35 ; CHECK: strh [[W0]], [x0]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td56 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
66 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
101 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
104 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
145 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
150 [W0, W1, W2, W3, W4, W5, W6]>>>,
155 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
202 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
204 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
205 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td60 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
70 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
107 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
110 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
159 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
164 [W0, W1, W2, W3, W4, W5, W6]>>>,
169 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
217 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
219 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
220 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
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DAArch64CollectLOH.cpp261 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
264 if (AArch64::W0 <= Reg && Reg <= AArch64::W30) in mapRegToGPRIndex()
265 return Reg - AArch64::W0; in mapRegToGPRIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFCallingConv.td31 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [R0]>>,
32 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
/external/mesa3d/src/intel/isl/
Disl.c1132 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_slice0_extent_sa_gen4_2d() local
1136 uint32_t W = isl_minify(W0, l); in isl_calc_phys_slice0_extent_sa_gen4_2d()
1228 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gen4_3d() local
1234 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); in isl_calc_phys_total_extent_el_gen4_3d()
1281 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gen6_stencil_hiz() local
1294 const uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gen6_stencil_hiz()
1339 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gen9_1d() local
1342 uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gen9_1d()
2324 const uint32_t W0 = surf->phys_level0_sa.width; in get_image_offset_sa_gen4_2d() local
2335 uint32_t W = isl_minify(W0, l); in get_image_offset_sa_gen4_2d()
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/external/deqp/framework/delibs/cmake/
DCFlags.cmake77 set(DE_3RD_PARTY_C_FLAGS "${CMAKE_C_FLAGS} ${MSC_BASE_FLAGS} /W0")
78 set(DE_3RD_PARTY_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${MSC_BASE_FLAGS} /EHsc /W0")
/external/libyuv/files/util/
Dssim.cc72 } W0 = MAKE_WEIGHT(0), W1 = MAKE_WEIGHT(1), W2 = MAKE_WEIGHT(2), variable
273 LOAD_LINE_PAIR(0, W0); in GetSSIMFullKernel()
279 LOAD_LINE_PAIR(6, W0); in GetSSIMFullKernel()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc137 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
179 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
381 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
398 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
423 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
737 if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
744 if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
857 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
873 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
966 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
[all …]

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