Searched refs:cci_enable_snoop_dvm_reqs (Results 1 – 18 of 18) sorted by relevance
108 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_pwr_domain_on_finish()251 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()263 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()
341 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in bl31_early_platform_setup2()
65 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_on_finish()149 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_suspend_finish()
85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in bl31_early_platform_setup2()
42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
50 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl1_early_platform_setup()
52 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in bl31_early_platform_setup2()
41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
59 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
121 void cci_enable_snoop_dvm_reqs(unsigned int master_id);
133 void cci_enable_snoop_dvm_reqs(unsigned int master_id) in cci_enable_snoop_dvm_reqs() function
90 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in bl31_early_platform_setup2()
85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in hikey960_pwr_domain_on_finish()
381 cci_enable_snoop_dvm_reqs(master); in fvp_interconnect_enable()
116 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()