| /external/llvm/test/CodeGen/X86/ |
| D | cmpxchg-i128-i1.ll | 5 ; CHECK: cmpxchg16b
16 ; CHECK: cmpxchg16b
33 ; Can't use the flags here because cmpxchg16b only sets ZF.
36 ; CHECK: cmpxchg16b
48 ; CHECK: cmpxchg16b
61 ; CHECK: cmpxchg16b
|
| D | atomic128.ll | 16 ; CHECK: cmpxchg16b (%rdi)
38 ; CHECK: cmpxchg16b (%rdi)
61 ; CHECK: cmpxchg16b (%rdi)
85 ; CHECK: cmpxchg16b (%rdi)
109 ; CHECK: cmpxchg16b (%rdi)
134 ; CHECK: cmpxchg16b (%rdi)
159 ; CHECK: cmpxchg16b (%rdi)
184 ; CHECK: cmpxchg16b (%rdi)
209 ; CHECK: cmpxchg16b (%rdi)
227 ; CHECK: cmpxchg16b (%rdi)
[all …]
|
| D | cmpxchg16b.ll | 7 ; CHECK: lock cmpxchg16b
|
| D | base-pointer-and-cmpxchg.ll | 23 ; cmpxchg16b is set.
37 ; USE_BASE-NEXT: cmpxchg16b
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | cmpxchg-i128-i1.ll | 14 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
34 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
60 ; Can't use the flags here because cmpxchg16b only sets ZF.
72 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
96 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
121 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
131 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
|
| D | atomic128.ll | 19 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
45 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
73 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
101 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
129 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
160 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
191 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
222 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
253 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
275 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
[all …]
|
| D | inline-asm-A-constraint.ll | 14 …%2 = tail call i128 asm sideeffect "lock; cmpxchg16b $1", "=A,=*m,{cx},{bx},0,*m,~{dirflag},~{fpsr…
23 ; CHECK-NEXT: cmpxchg16b
|
| D | base-pointer-and-cmpxchg.ll | 23 ; cmpxchg16b is set.
37 ; USE_BASE-NEXT: cmpxchg16b
|
| D | cmpxchg16b.ll | 13 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
|
| D | schedule-x86_64.ll | 4642 ; GENERIC-NEXT: cmpxchg16b (%rdi) # sched: [6:1.00]
4650 ; ATOM-NEXT: cmpxchg16b (%rdi) # sched: [22:11.00]
4658 ; SLM-NEXT: cmpxchg16b (%rdi) # sched: [4:2.00]
4666 ; SANDY-NEXT: cmpxchg16b (%rdi) # sched: [6:1.00]
4674 ; HASWELL-NEXT: cmpxchg16b (%rdi) # sched: [22:4.00]
4682 ; BROADWELL-NEXT: cmpxchg16b (%rdi) # sched: [21:4.00]
4690 ; SKYLAKE-NEXT: cmpxchg16b (%rdi) # sched: [23:4.00]
4698 ; SKX-NEXT: cmpxchg16b (%rdi) # sched: [23:4.00]
4706 ; BTVER2-NEXT: cmpxchg16b (%rdi) # sched: [4:1.00]
4714 ; ZNVER1-NEXT: cmpxchg16b (%rdi) # sched: [100:0.25]
[all …]
|
| /external/cpuinfo/src/x86/nacl/ |
| D | isa.c | 220 …isa.cmpxchg16b = !nacl_irt_dyncode.dyncode_create((void*) code_segment, cmpxchg16b_bundle, NACL_CO… in cpuinfo_x86_nacl_detect_isa()
|
| /external/cpuinfo/include/ |
| D | cpuinfo.h | 702 bool cmpxchg16b; member
1248 return cpuinfo_isa.cmpxchg16b; in cpuinfo_has_x86_cmpxchg16b()
|
| /external/cpuinfo/src/x86/ |
| D | isa.c | 541 isa.cmpxchg16b = !!(basic_info.ecx & UINT32_C(0x00002000)); in cpuinfo_x86_detect_isa()
|
| /external/llvm/docs/ |
| D | ScudoHardenedAllocator.rst | 51 platform support such as the cmpxchg16b instruction). This is important as two
|
| /external/cpuinfo/test/mock/ |
| D | zenfone-2e.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| D | zenfone-2.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| D | alldocube-iwork8.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| D | zenfone-c.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| D | memo-pad-7.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| D | leagoo-t5c.cc | 457 TEST(ISA, cmpxchg16b) { in TEST() argument
|
| /external/llvm/lib/Target/X86/ |
| D | X86.td | 96 "64-bit with cmpxchg16b",
|
| D | X86InstrCompiler.td | 797 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
810 !strconcat("cmpxchg16b", "\t$ptr"),
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86.td | 99 "64-bit with cmpxchg16b",
|
| D | X86InstrCompiler.td | 827 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
839 !strconcat("cmpxchg16b", "\t$ptr"),
|
| /external/elfutils/libcpu/defs/ |
| D | i386 | 152 `# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m}
|