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Searched refs:dcc_offset (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/amd/common/
Dac_surface.c566 surf_level->dcc_offset = 0; in gfx6_compute_level()
581 surf_level->dcc_offset = surf->dcc_size; in gfx6_compute_level()
583 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; in gfx6_compute_level()
2111 surf->dcc_offset = surf->display_dcc_offset = 0; in ac_compute_surface()
2150 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); in ac_compute_surface()
2151 surf->total_size = surf->dcc_offset + surf->dcc_size; in ac_compute_surface()
2161 surf->dcc_offset = 0; in ac_surface_zero_dcc_fields()
2265 uint64_t dcc_offset = 0; in ac_surface_get_bo_metadata() local
2267 if (surf->dcc_offset) { in ac_surface_get_bo_metadata()
2268 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->dcc_offset; in ac_surface_get_bo_metadata()
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Dac_surface.h87 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member
253 uint64_t dcc_offset; member
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c220 uint64_t dcc_offset, clear_size; in vi_dcc_clear_level() local
226 dcc_offset = 0; in vi_dcc_clear_level()
229 dcc_offset = tex->surface.dcc_offset; in vi_dcc_clear_level()
257 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset; in vi_dcc_clear_level()
261 si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size, &clear_value, 4, SI_COHERENCY_CB_META, in vi_dcc_clear_level()
Dsi_texture.c379 return tex->surface.dcc_offset && in si_can_disable_dcc()
514 tex->surface.dcc_offset = new_tex->surface.dcc_offset; in si_reallocate_texture_inplace()
544 assert(!tex->surface.dcc_offset); in si_reallocate_texture_inplace()
587 return tex->surface.is_displayable && tex->surface.dcc_offset; in si_has_displayable_dcc()
716 if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->surface.dcc_offset) || in si_texture_get_handle()
727 (tex->cmask_buffer || tex->surface.dcc_offset)) { in si_texture_get_handle()
874 if (tex->surface.dcc_offset) { in si_print_texture_info()
878 tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment, in si_print_texture_info()
921 if (tex->surface.dcc_offset) { in si_print_texture_info()
923 tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment); in si_print_texture_info()
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Dsi_compute_blit.c630 assert(tex->surface.dcc_offset && tex->surface.dcc_offset <= UINT_MAX); in si_retile_dcc()
644 img[1].u.buf.offset = tex->surface.dcc_offset; in si_retile_dcc()
Dsi_descriptors.c338 (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset; in si_set_mutable_tex_desc_fields()
341 meta_va += base_level_info->dcc_offset; in si_set_mutable_tex_desc_fields()
377 if (tex->surface.dcc_offset) in si_set_mutable_tex_desc_fields()
415 if (tex->surface.dcc_offset) in si_set_mutable_tex_desc_fields()
488 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset)); in color_needs_decompression()
Dsi_blit.c1266 if (!tex->surface.dcc_offset || !sctx->has_graphics) in si_decompress_dcc()
1288 si_clear_buffer(sctx, ptex, tex->surface.dcc_offset, in si_decompress_dcc()
Dsi_pipe.h1588 return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels; in vi_dcc_enabled()
Dsi_state.c2951 ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset) >> in si_emit_framebuffer_state()
3006 if (tex->surface.dcc_offset) in si_emit_framebuffer_state()
3057 cb_dcc_base += level_info->dcc_offset >> 8; in si_emit_framebuffer_state()
/external/mesa3d/src/amd/vulkan/
Dradv_image.c659 meta_va = gpu_address + plane->surface.dcc_offset; in si_set_mutable_tex_desc_fields()
661 meta_va += base_level_info->dcc_offset; in si_set_mutable_tex_desc_fields()
696 if (plane->surface.dcc_offset) in si_set_mutable_tex_desc_fields()
725 if (plane->surface.dcc_offset) in si_set_mutable_tex_desc_fields()
1030 if (image->planes[0].surface.dcc_offset) { in si_make_texture_descriptor()
1206 desc[7] = image->planes[0].surface.dcc_offset >> 8; in radv_query_opaque_metadata()
Dradv_meta_clear.c1532 uint64_t offset = image->offset + image->planes[0].surface.dcc_offset; in radv_clear_dcc()
1550 offset += surf_level->dcc_offset + in radv_clear_dcc()
Dradv_device.c6751 if (surf->dcc_offset) in radv_initialise_color_surface()
6801 va += surf->dcc_offset; in radv_initialise_color_surface()
6805 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset; in radv_initialise_color_surface()
Dradv_cmd_buffer.c6045 size = surf_level->dcc_offset + dcc_fast_clear_size; in radv_initialize_dcc()
6052 image->offset + image->planes[0].surface.dcc_offset + size, in radv_initialize_dcc()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3235 - radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly