| /external/u-boot/board/gardena/smart-gateway-at91sam/ |
| D | spl.c | 80 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
82 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
84 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
90 ddr2->rtr = 0x411; in ddr2_conf()
92 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
101 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
106 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
117 struct atmel_mpddrc_config ddr2; in mem_init() local
120 ddr2_conf(&ddr2); in mem_init()
134 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /external/u-boot/board/atmel/sama5d3_xplained/ |
| D | sama5d3_xplained.c | 134 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
136 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
138 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
150 ddr2->rtr = 0x411; in ddr2_conf()
152 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
161 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
166 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
175 struct atmel_mpddrc_config ddr2; in mem_init() local
177 ddr2_conf(&ddr2); in mem_init()
184 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
|
| /external/u-boot/board/laird/wb45n/ |
| D | wb45n.c | 146 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
148 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
150 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
156 ddr2->rtr = 0x411; in ddr2_conf()
158 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
167 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
172 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
182 struct atmel_mpddrc_config ddr2; in mem_init() local
185 ddr2_conf(&ddr2); in mem_init()
196 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
|
| /external/u-boot/board/laird/wb50n/ |
| D | wb50n.c | 141 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
143 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
145 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | in ddr2_conf()
152 ddr2->rtr = 0x411; in ddr2_conf()
154 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
163 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
168 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
177 struct atmel_mpddrc_config ddr2; in mem_init() local
179 ddr2_conf(&ddr2); in mem_init()
188 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
|
| /external/u-boot/board/atmel/at91sam9x5ek/ |
| D | at91sam9x5ek.c | 153 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
155 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
157 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
163 ddr2->rtr = 0x411; in ddr2_conf()
165 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
174 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
179 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
190 struct atmel_mpddrc_config ddr2; in mem_init() local
193 ddr2_conf(&ddr2); in mem_init()
207 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
|
| /external/u-boot/board/atmel/sama5d4_xplained/ |
| D | sama5d4_xplained.c | 154 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
156 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
158 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
166 ddr2->rtr = 0x2b0; in ddr2_conf()
168 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
177 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
182 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
191 struct atmel_mpddrc_config ddr2; in mem_init() local
193 ddr2_conf(&ddr2); in mem_init()
200 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
|
| /external/u-boot/board/atmel/sama5d4ek/ |
| D | sama5d4ek.c | 140 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
142 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
144 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
151 ddr2->rtr = 0x2b0; in ddr2_conf()
153 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
162 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
167 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
176 struct atmel_mpddrc_config ddr2; in mem_init() local
180 ddr2_conf(&ddr2); in mem_init()
200 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
|
| /external/u-boot/board/mini-box/picosam9g45/ |
| D | picosam9g45.c | 50 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
52 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
54 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
59 ddr2->rtr = 0x24b; in ddr2_conf()
61 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
70 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
75 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
84 struct atmel_mpddrc_config ddr2; in mem_init() local
87 ddr2_conf(&ddr2); in mem_init()
98 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
[all …]
|
| /external/u-boot/board/siemens/corvus/ |
| D | board.c | 136 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
138 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
140 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
145 ddr2->rtr = 0x24b; in ddr2_conf()
147 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
156 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
161 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
169 struct atmel_mpddrc_config ddr2; in mem_init() local
171 ddr2_conf(&ddr2); in mem_init()
176 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
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| /external/u-boot/board/atmel/at91sam9m10g45ek/ |
| D | at91sam9m10g45ek.c | 95 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
97 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
99 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
104 ddr2->rtr = 0x24b; in ddr2_conf()
106 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
115 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
120 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
128 struct atmel_mpddrc_config ddr2; in mem_init() local
130 ddr2_conf(&ddr2); in mem_init()
135 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
|
| /external/u-boot/board/atmel/sama5d3xek/ |
| D | sama5d3xek.c | 207 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
209 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
211 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
223 ddr2->rtr = 0x411; in ddr2_conf()
225 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
234 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
239 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
248 struct atmel_mpddrc_config ddr2; in mem_init() local
250 ddr2_conf(&ddr2); in mem_init()
257 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
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| /external/u-boot/board/atmel/at91sam9n12ek/ |
| D | at91sam9n12ek.c | 237 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
239 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
241 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
247 ddr2->rtr = 0x411; in ddr2_conf()
249 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
258 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
263 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
273 struct atmel_mpddrc_config ddr2; in mem_init() local
276 ddr2_conf(&ddr2); in mem_init()
290 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); in mem_init()
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| /external/u-boot/drivers/ddr/microchip/ |
| D | Makefile | 4 obj-$(CONFIG_MACH_PIC32) += ddr2.o
|
| /external/hyphenation-patterns/cy/ |
| D | hyph-cy.pat.txt | 1300 ddr2
|