1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <vsprintf.h>
11 #include <asm/io.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/at91sam9g45_matrix.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
18 #include <lcd.h>
19 #include <linux/mtd/rawnand.h>
20 #include <atmel_lcdc.h>
21 #include <asm/mach-types.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 /* ------------------------------------------------------------------------- */
26 /*
27 * Miscelaneous platform dependent initialisations
28 */
29
30 #ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init(void)31 void at91sam9m10g45ek_nand_hw_init(void)
32 {
33 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
34 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
35 unsigned long csa;
36
37 /* Enable CS3 */
38 csa = readl(&matrix->ebicsa);
39 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
40 writel(csa, &matrix->ebicsa);
41
42 /* Configure SMC CS3 for NAND/SmartMedia */
43 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
44 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
45 &smc->cs[3].setup);
46 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
47 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
48 &smc->cs[3].pulse);
49 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
50 &smc->cs[3].cycle);
51 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
52 AT91_SMC_MODE_EXNW_DISABLE |
53 #ifdef CONFIG_SYS_NAND_DBW_16
54 AT91_SMC_MODE_DBW_16 |
55 #else /* CONFIG_SYS_NAND_DBW_8 */
56 AT91_SMC_MODE_DBW_8 |
57 #endif
58 AT91_SMC_MODE_TDF_CYCLE(3),
59 &smc->cs[3].mode);
60
61 at91_periph_clk_enable(ATMEL_ID_PIOC);
62
63 /* Configure RDY/BSY */
64 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
65
66 /* Enable NandFlash */
67 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
68 }
69 #endif
70
71 #if defined(CONFIG_SPL_BUILD)
72 #include <spl.h>
73 #include <nand.h>
74
at91_spl_board_init(void)75 void at91_spl_board_init(void)
76 {
77 /*
78 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
79 * test mode, so it needs do some action to exit test mode.
80 */
81 at91_periph_clk_enable(ATMEL_ID_PIODE);
82 at91_set_gpio_output(AT91_PIN_PD7, 0);
83 at91_set_gpio_output(AT91_PIN_PD8, 0);
84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
86
87 #ifdef CONFIG_SD_BOOT
88 at91_mci_hw_init();
89 #elif CONFIG_NAND_BOOT
90 at91sam9m10g45ek_nand_hw_init();
91 #endif
92 }
93
94 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)95 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
96 {
97 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
98
99 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
100 ATMEL_MPDDRC_CR_NR_ROW_14 |
101 ATMEL_MPDDRC_CR_DQMS_SHARED |
102 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
103
104 ddr2->rtr = 0x24b;
105
106 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
107 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
108 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
109 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
110 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
111 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
112 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
113 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
114
115 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
116 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
117 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
118 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
119
120 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
121 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
122 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
123 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
124 }
125
mem_init(void)126 void mem_init(void)
127 {
128 struct atmel_mpddrc_config ddr2;
129
130 ddr2_conf(&ddr2);
131
132 at91_system_clk_enable(AT91_PMC_DDR);
133
134 /* DDRAM2 Controller initialize */
135 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
136 }
137 #endif
138
139 #ifdef CONFIG_CMD_USB
at91sam9m10g45ek_usb_hw_init(void)140 static void at91sam9m10g45ek_usb_hw_init(void)
141 {
142 at91_periph_clk_enable(ATMEL_ID_PIODE);
143
144 at91_set_gpio_output(AT91_PIN_PD1, 0);
145 at91_set_gpio_output(AT91_PIN_PD3, 0);
146 }
147 #endif
148
149 #ifdef CONFIG_LCD
150
151 vidinfo_t panel_info = {
152 .vl_col = 480,
153 .vl_row = 272,
154 .vl_clk = 9000000,
155 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
156 ATMEL_LCDC_INVFRAME_NORMAL,
157 .vl_bpix = 3,
158 .vl_tft = 1,
159 .vl_hsync_len = 45,
160 .vl_left_margin = 1,
161 .vl_right_margin = 1,
162 .vl_vsync_len = 1,
163 .vl_upper_margin = 40,
164 .vl_lower_margin = 1,
165 .mmio = ATMEL_BASE_LCDC,
166 };
167
168
lcd_enable(void)169 void lcd_enable(void)
170 {
171 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
172 }
173
lcd_disable(void)174 void lcd_disable(void)
175 {
176 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
177 }
178
at91sam9m10g45ek_lcd_hw_init(void)179 static void at91sam9m10g45ek_lcd_hw_init(void)
180 {
181 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
182 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
183 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
184 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
185 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
186
187 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
188 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
189 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
190 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
191 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
192 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
193 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
194 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
195 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
196 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
197 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
198 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
199 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
200 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
201 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
202 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
203 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
204 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
205 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
206 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
207 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
208 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
209 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
210 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
211
212 at91_periph_clk_enable(ATMEL_ID_LCDC);
213
214 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
215 }
216
217 #ifdef CONFIG_LCD_INFO
218 #include <nand.h>
219 #include <version.h>
220
lcd_show_board_info(void)221 void lcd_show_board_info(void)
222 {
223 ulong dram_size, nand_size;
224 int i;
225 char temp[32];
226
227 lcd_printf ("%s\n", U_BOOT_VERSION);
228 lcd_printf ("(C) 2008 ATMEL Corp\n");
229 lcd_printf ("at91support@atmel.com\n");
230 lcd_printf ("%s CPU at %s MHz\n",
231 ATMEL_CPU_NAME,
232 strmhz(temp, get_cpu_clk_rate()));
233
234 dram_size = 0;
235 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
236 dram_size += gd->bd->bi_dram[i].size;
237 nand_size = 0;
238 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
239 nand_size += get_nand_dev_by_index(i)->size;
240 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
241 dram_size >> 20,
242 nand_size >> 20 );
243 }
244 #endif /* CONFIG_LCD_INFO */
245 #endif
246
247 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)248 void board_debug_uart_init(void)
249 {
250 at91_seriald_hw_init();
251 }
252 #endif
253
254 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)255 int board_early_init_f(void)
256 {
257 #ifdef CONFIG_DEBUG_UART
258 debug_uart_init();
259 #endif
260 return 0;
261 }
262 #endif
263
board_init(void)264 int board_init(void)
265 {
266 /* arch number of AT91SAM9M10G45EK-Board */
267 #ifdef CONFIG_AT91SAM9M10G45EK
268 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
269 #elif defined CONFIG_AT91SAM9G45EKES
270 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
271 #endif
272
273 /* adress of boot parameters */
274 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
275
276 #ifdef CONFIG_CMD_NAND
277 at91sam9m10g45ek_nand_hw_init();
278 #endif
279 #ifdef CONFIG_CMD_USB
280 at91sam9m10g45ek_usb_hw_init();
281 #endif
282 #ifdef CONFIG_LCD
283 at91sam9m10g45ek_lcd_hw_init();
284 #endif
285 return 0;
286 }
287
dram_init(void)288 int dram_init(void)
289 {
290 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
291 CONFIG_SYS_SDRAM_SIZE);
292 return 0;
293 }
294
295 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)296 void reset_phy(void)
297 {
298 }
299 #endif
300