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Searched refs:devcfg_base (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/fpga/
Dzynqpl.c160 writel((u32)srcbuf, &devcfg_base->dma_src_addr); in zynq_dma_transfer()
161 writel(dstbuf, &devcfg_base->dma_dst_addr); in zynq_dma_transfer()
162 writel(srclen, &devcfg_base->dma_src_len); in zynq_dma_transfer()
163 writel(dstlen, &devcfg_base->dma_dst_len); in zynq_dma_transfer()
165 isr_status = readl(&devcfg_base->int_sts); in zynq_dma_transfer()
174 readl(&devcfg_base->write_count)); in zynq_dma_transfer()
176 readl(&devcfg_base->read_count)); in zynq_dma_transfer()
185 isr_status = readl(&devcfg_base->int_sts); in zynq_dma_transfer()
191 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); in zynq_dma_transfer()
202 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); in zynq_dma_xfer_init()
[all …]
/external/u-boot/arch/arm/mach-zynq/
Dcpu.c52 writel(0x757BDF0D, &devcfg_base->unlock); in arch_cpu_init()
53 writel(0xFFFFFFFF, &devcfg_base->rom_shadow); in arch_cpu_init()
76 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) in zynq_get_silicon_version()
/external/u-boot/arch/arm/mach-zynq/include/mach/
Dhardware.h113 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR) macro