1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
5 * (C) Copyright 2012
6 * Joe Hershberger <joe.hershberger@ni.com>
7 */
8
9 #include <common.h>
10 #include <console.h>
11 #include <cpu_func.h>
12 #include <asm/io.h>
13 #include <fs.h>
14 #include <zynqpl.h>
15 #include <linux/sizes.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/sys_proto.h>
18
19 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
20 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
21 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
22 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
23 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
24 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
25 #define DEVCFG_ISR_DMA_DONE 0x00002000
26 #define DEVCFG_ISR_PCFG_DONE 0x00000004
27 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
28 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
29 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
30 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
31 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
32 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
33 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
34
35 #ifndef CONFIG_SYS_FPGA_WAIT
36 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
37 #endif
38
39 #ifndef CONFIG_SYS_FPGA_PROG_TIME
40 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
41 #endif
42
43 #define DUMMY_WORD 0xffffffff
44
45 /* Xilinx binary format header */
46 static const u32 bin_format[] = {
47 DUMMY_WORD, /* Dummy words */
48 DUMMY_WORD,
49 DUMMY_WORD,
50 DUMMY_WORD,
51 DUMMY_WORD,
52 DUMMY_WORD,
53 DUMMY_WORD,
54 DUMMY_WORD,
55 0x000000bb, /* Sync word */
56 0x11220044, /* Sync word */
57 DUMMY_WORD,
58 DUMMY_WORD,
59 0xaa995566, /* Sync word */
60 };
61
62 #define SWAP_NO 1
63 #define SWAP_DONE 2
64
65 /*
66 * Load the whole word from unaligned buffer
67 * Keep in your mind that it is byte loading on little-endian system
68 */
load_word(const void * buf,u32 swap)69 static u32 load_word(const void *buf, u32 swap)
70 {
71 u32 word = 0;
72 u8 *bitc = (u8 *)buf;
73 int p;
74
75 if (swap == SWAP_NO) {
76 for (p = 0; p < 4; p++) {
77 word <<= 8;
78 word |= bitc[p];
79 }
80 } else {
81 for (p = 3; p >= 0; p--) {
82 word <<= 8;
83 word |= bitc[p];
84 }
85 }
86
87 return word;
88 }
89
check_header(const void * buf)90 static u32 check_header(const void *buf)
91 {
92 u32 i, pattern;
93 int swap = SWAP_NO;
94 u32 *test = (u32 *)buf;
95
96 debug("%s: Let's check bitstream header\n", __func__);
97
98 /* Checking that passing bin is not a bitstream */
99 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
100 pattern = load_word(&test[i], swap);
101
102 /*
103 * Bitstreams in binary format are swapped
104 * compare to regular bistream.
105 * Do not swap dummy word but if swap is done assume
106 * that parsing buffer is binary format
107 */
108 if ((__swab32(pattern) != DUMMY_WORD) &&
109 (__swab32(pattern) == bin_format[i])) {
110 pattern = __swab32(pattern);
111 swap = SWAP_DONE;
112 debug("%s: data swapped - let's swap\n", __func__);
113 }
114
115 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
116 (u32)&test[i], pattern, bin_format[i]);
117 if (pattern != bin_format[i]) {
118 debug("%s: Bitstream is not recognized\n", __func__);
119 return 0;
120 }
121 }
122 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
123 (u32)buf, swap == SWAP_NO ? "without" : "with");
124
125 return swap;
126 }
127
check_data(u8 * buf,size_t bsize,u32 * swap)128 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
129 {
130 u32 word, p = 0; /* possition */
131
132 /* Because buf doesn't need to be aligned let's read it by chars */
133 for (p = 0; p < bsize; p++) {
134 word = load_word(&buf[p], SWAP_NO);
135 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
136
137 /* Find the first bitstream dummy word */
138 if (word == DUMMY_WORD) {
139 debug("%s: Found dummy word at position %x/%x\n",
140 __func__, p, (u32)&buf[p]);
141 *swap = check_header(&buf[p]);
142 if (*swap) {
143 /* FIXME add full bitstream checking here */
144 return &buf[p];
145 }
146 }
147 /* Loop can be huge - support CTRL + C */
148 if (ctrlc())
149 return NULL;
150 }
151 return NULL;
152 }
153
zynq_dma_transfer(u32 srcbuf,u32 srclen,u32 dstbuf,u32 dstlen)154 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
155 {
156 unsigned long ts;
157 u32 isr_status;
158
159 /* Set up the transfer */
160 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
161 writel(dstbuf, &devcfg_base->dma_dst_addr);
162 writel(srclen, &devcfg_base->dma_src_len);
163 writel(dstlen, &devcfg_base->dma_dst_len);
164
165 isr_status = readl(&devcfg_base->int_sts);
166
167 /* Polling the PCAP_INIT status for Set */
168 ts = get_timer(0);
169 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
170 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
171 debug("%s: Error: isr = 0x%08X\n", __func__,
172 isr_status);
173 debug("%s: Write count = 0x%08X\n", __func__,
174 readl(&devcfg_base->write_count));
175 debug("%s: Read count = 0x%08X\n", __func__,
176 readl(&devcfg_base->read_count));
177
178 return FPGA_FAIL;
179 }
180 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
181 printf("%s: Timeout wait for DMA to complete\n",
182 __func__);
183 return FPGA_FAIL;
184 }
185 isr_status = readl(&devcfg_base->int_sts);
186 }
187
188 debug("%s: DMA transfer is done\n", __func__);
189
190 /* Clear out the DMA status */
191 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
192
193 return FPGA_SUCCESS;
194 }
195
zynq_dma_xfer_init(bitstream_type bstype)196 static int zynq_dma_xfer_init(bitstream_type bstype)
197 {
198 u32 status, control, isr_status;
199 unsigned long ts;
200
201 /* Clear loopback bit */
202 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
203
204 if (bstype != BIT_PARTIAL) {
205 zynq_slcr_devcfg_disable();
206
207 /* Setting PCFG_PROG_B signal to high */
208 control = readl(&devcfg_base->ctrl);
209 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
210
211 /*
212 * Delay is required if AES efuse is selected as
213 * key source.
214 */
215 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
216 mdelay(5);
217
218 /* Setting PCFG_PROG_B signal to low */
219 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
220
221 /*
222 * Delay is required if AES efuse is selected as
223 * key source.
224 */
225 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
226 mdelay(5);
227
228 /* Polling the PCAP_INIT status for Reset */
229 ts = get_timer(0);
230 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
231 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
232 printf("%s: Timeout wait for INIT to clear\n",
233 __func__);
234 return FPGA_FAIL;
235 }
236 }
237
238 /* Setting PCFG_PROG_B signal to high */
239 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
240
241 /* Polling the PCAP_INIT status for Set */
242 ts = get_timer(0);
243 while (!(readl(&devcfg_base->status) &
244 DEVCFG_STATUS_PCFG_INIT)) {
245 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
246 printf("%s: Timeout wait for INIT to set\n",
247 __func__);
248 return FPGA_FAIL;
249 }
250 }
251 }
252
253 isr_status = readl(&devcfg_base->int_sts);
254
255 /* Clear it all, so if Boot ROM comes back, it can proceed */
256 writel(0xFFFFFFFF, &devcfg_base->int_sts);
257
258 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
259 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
260
261 /* If RX FIFO overflow, need to flush RX FIFO first */
262 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
263 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
264 writel(0xFFFFFFFF, &devcfg_base->int_sts);
265 }
266 return FPGA_FAIL;
267 }
268
269 status = readl(&devcfg_base->status);
270
271 debug("%s: Status = 0x%08X\n", __func__, status);
272
273 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
274 debug("%s: Error: device busy\n", __func__);
275 return FPGA_FAIL;
276 }
277
278 debug("%s: Device ready\n", __func__);
279
280 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
281 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
282 /* Error state, transfer cannot occur */
283 debug("%s: ISR indicates error\n", __func__);
284 return FPGA_FAIL;
285 } else {
286 /* Clear out the status */
287 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
288 }
289 }
290
291 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
292 /* Clear the count of completed DMA transfers */
293 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
294 }
295
296 return FPGA_SUCCESS;
297 }
298
zynq_align_dma_buffer(u32 * buf,u32 len,u32 swap)299 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
300 {
301 u32 *new_buf;
302 u32 i;
303
304 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
305 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
306
307 /*
308 * This might be dangerous but permits to flash if
309 * ARCH_DMA_MINALIGN is greater than header size
310 */
311 if (new_buf > buf) {
312 debug("%s: Aligned buffer is after buffer start\n",
313 __func__);
314 new_buf -= ARCH_DMA_MINALIGN;
315 }
316 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
317 (u32)buf, (u32)new_buf, swap);
318
319 for (i = 0; i < (len/4); i++)
320 new_buf[i] = load_word(&buf[i], swap);
321
322 buf = new_buf;
323 } else if (swap != SWAP_DONE) {
324 /* For bitstream which are aligned */
325 u32 *new_buf = (u32 *)buf;
326
327 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
328 swap);
329
330 for (i = 0; i < (len/4); i++)
331 new_buf[i] = load_word(&buf[i], swap);
332 }
333
334 return buf;
335 }
336
zynq_validate_bitstream(xilinx_desc * desc,const void * buf,size_t bsize,u32 blocksize,u32 * swap,bitstream_type * bstype)337 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
338 size_t bsize, u32 blocksize, u32 *swap,
339 bitstream_type *bstype)
340 {
341 u32 *buf_start;
342 u32 diff;
343
344 buf_start = check_data((u8 *)buf, blocksize, swap);
345
346 if (!buf_start)
347 return FPGA_FAIL;
348
349 /* Check if data is postpone from start */
350 diff = (u32)buf_start - (u32)buf;
351 if (diff) {
352 printf("%s: Bitstream is not validated yet (diff %x)\n",
353 __func__, diff);
354 return FPGA_FAIL;
355 }
356
357 if ((u32)buf < SZ_1M) {
358 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
359 __func__, (u32)buf);
360 return FPGA_FAIL;
361 }
362
363 if (zynq_dma_xfer_init(*bstype))
364 return FPGA_FAIL;
365
366 return 0;
367 }
368
zynq_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)369 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
370 bitstream_type bstype)
371 {
372 unsigned long ts; /* Timestamp */
373 u32 isr_status, swap;
374
375 /*
376 * send bsize inplace of blocksize as it was not a bitstream
377 * in chunks
378 */
379 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
380 &bstype))
381 return FPGA_FAIL;
382
383 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
384
385 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
386 debug("%s: Size = %zu\n", __func__, bsize);
387
388 /* flush(clean & invalidate) d-cache range buf */
389 flush_dcache_range((u32)buf, (u32)buf +
390 roundup(bsize, ARCH_DMA_MINALIGN));
391
392 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
393 return FPGA_FAIL;
394
395 isr_status = readl(&devcfg_base->int_sts);
396 /* Check FPGA configuration completion */
397 ts = get_timer(0);
398 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
399 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
400 printf("%s: Timeout wait for FPGA to config\n",
401 __func__);
402 return FPGA_FAIL;
403 }
404 isr_status = readl(&devcfg_base->int_sts);
405 }
406
407 debug("%s: FPGA config done\n", __func__);
408
409 if (bstype != BIT_PARTIAL)
410 zynq_slcr_devcfg_enable();
411
412 puts("INFO:post config was not run, please run manually if needed\n");
413
414 return FPGA_SUCCESS;
415 }
416
417 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
zynq_loadfs(xilinx_desc * desc,const void * buf,size_t bsize,fpga_fs_info * fsinfo)418 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
419 fpga_fs_info *fsinfo)
420 {
421 unsigned long ts; /* Timestamp */
422 u32 isr_status, swap;
423 u32 partialbit = 0;
424 loff_t blocksize, actread;
425 loff_t pos = 0;
426 int fstype;
427 char *interface, *dev_part;
428 const char *filename;
429
430 blocksize = fsinfo->blocksize;
431 interface = fsinfo->interface;
432 dev_part = fsinfo->dev_part;
433 filename = fsinfo->filename;
434 fstype = fsinfo->fstype;
435
436 if (fs_set_blk_dev(interface, dev_part, fstype))
437 return FPGA_FAIL;
438
439 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
440 return FPGA_FAIL;
441
442 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
443 &partialbit))
444 return FPGA_FAIL;
445
446 dcache_disable();
447
448 do {
449 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
450
451 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
452 0xffffffff, 0))
453 return FPGA_FAIL;
454
455 bsize -= blocksize;
456 pos += blocksize;
457
458 if (fs_set_blk_dev(interface, dev_part, fstype))
459 return FPGA_FAIL;
460
461 if (bsize > blocksize) {
462 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
463 return FPGA_FAIL;
464 } else {
465 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
466 return FPGA_FAIL;
467 }
468 } while (bsize > blocksize);
469
470 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
471
472 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
473 return FPGA_FAIL;
474
475 dcache_enable();
476
477 isr_status = readl(&devcfg_base->int_sts);
478
479 /* Check FPGA configuration completion */
480 ts = get_timer(0);
481 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
482 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
483 printf("%s: Timeout wait for FPGA to config\n",
484 __func__);
485 return FPGA_FAIL;
486 }
487 isr_status = readl(&devcfg_base->int_sts);
488 }
489
490 debug("%s: FPGA config done\n", __func__);
491
492 if (!partialbit)
493 zynq_slcr_devcfg_enable();
494
495 return FPGA_SUCCESS;
496 }
497 #endif
498
499 struct xilinx_fpga_op zynq_op = {
500 .load = zynq_load,
501 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
502 .loadfs = zynq_loadfs,
503 #endif
504 };
505
506 #ifdef CONFIG_CMD_ZYNQ_AES
507 /*
508 * Load the encrypted image from src addr and decrypt the image and
509 * place it back the decrypted image into dstaddr.
510 */
zynq_decrypt_load(u32 srcaddr,u32 srclen,u32 dstaddr,u32 dstlen)511 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
512 {
513 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
514 printf("%s: src and dst addr should be > 1M\n",
515 __func__);
516 return FPGA_FAIL;
517 }
518
519 if (zynq_dma_xfer_init(BIT_NONE)) {
520 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
521 return FPGA_FAIL;
522 }
523
524 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
525 &devcfg_base->ctrl);
526
527 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
528 debug("%s: Size = %zu\n", __func__, srclen);
529
530 /* flush(clean & invalidate) d-cache range buf */
531 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
532 roundup(srclen << 2, ARCH_DMA_MINALIGN));
533 /*
534 * Flush destination address range only if image is not
535 * bitstream.
536 */
537 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
538 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
539
540 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
541 return FPGA_FAIL;
542
543 writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
544 &devcfg_base->ctrl);
545
546 return FPGA_SUCCESS;
547 }
548 #endif
549