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Searched refs:devid (Results 1 – 25 of 150) sorted by relevance

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/external/libdrm/intel/
Dintel_chipset.h55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) argument
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) argument
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) argument
171 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ argument
172 (devid) == PCI_CHIP_I915_GM || \
173 (devid) == PCI_CHIP_I945_GM || \
174 (devid) == PCI_CHIP_I945_GME || \
175 (devid) == PCI_CHIP_I965_GM || \
176 (devid) == PCI_CHIP_I965_GME || \
177 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
[all …]
Dintel_chipset.c47 drm_private bool intel_is_genx(unsigned int devid, int gen) in intel_is_genx() argument
57 if (p->device != devid) in intel_is_genx()
69 drm_private bool intel_get_genx(unsigned int devid, int *gen) in intel_get_genx() argument
75 if (p->device != devid) in intel_get_genx()
/external/igt-gpu-tools/lib/
Dintel_chipset.h77 const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
81 static inline unsigned intel_gen(uint16_t __attribute__((unused)) devid) { return false; } in intel_gen()
84 unsigned intel_gen(uint16_t devid) __attribute__((pure)); argument
87 unsigned intel_gt(uint16_t devid) __attribute__((pure));
140 #define IS_915G(devid) (intel_get_device_info(devid)->is_grantsdale) argument
141 #define IS_915GM(devid) (intel_get_device_info(devid)->is_alviso) argument
143 #define IS_915(devid) (IS_915G(devid) || IS_915GM(devid)) argument
145 #define IS_945G(devid) (intel_get_device_info(devid)->is_lakeport) argument
146 #define IS_945GM(devid) (intel_get_device_info(devid)->is_calistoga) argument
148 #define IS_945(devid) (IS_945G(devid) || \ argument
[all …]
Dintel_batchbuffer.c158 intel_batchbuffer_alloc(drm_intel_bufmgr *bufmgr, uint32_t devid) in intel_batchbuffer_alloc() argument
163 batch->devid = devid; in intel_batchbuffer_alloc()
164 batch->gen = intel_gen(devid); in intel_batchbuffer_alloc()
194 if (IS_GEN5(batch->devid)) { in flush_on_ring_common()
292 if (HAS_BLT_RING(batch->devid)) in intel_batchbuffer_flush()
827 igt_render_copyfunc_t igt_get_render_copyfunc(int devid) in igt_get_render_copyfunc() argument
831 if (IS_GEN2(devid)) in igt_get_render_copyfunc()
833 else if (IS_GEN3(devid)) in igt_get_render_copyfunc()
835 else if (IS_GEN4(devid) || IS_GEN5(devid)) in igt_get_render_copyfunc()
837 else if (IS_GEN6(devid)) in igt_get_render_copyfunc()
[all …]
Drendercopy_gen4.c98 static int gen4_max_vs_nr_urb_entries(uint32_t devid) in gen4_max_vs_nr_urb_entries() argument
100 return IS_GEN5(devid) ? 256 : 32; in gen4_max_vs_nr_urb_entries()
103 static int gen4_max_sf_nr_urb_entries(uint32_t devid) in gen4_max_sf_nr_urb_entries() argument
105 return IS_GEN5(devid) ? 128 : 64; in gen4_max_sf_nr_urb_entries()
108 static int gen4_urb_size(uint32_t devid) in gen4_urb_size() argument
110 return IS_GEN5(devid) ? 1024 : IS_G4X(devid) ? 384 : 256; in gen4_urb_size()
113 static int gen4_max_sf_threads(uint32_t devid) in gen4_max_sf_threads() argument
115 return IS_GEN5(devid) ? 48 : 24; in gen4_max_sf_threads()
118 static int gen4_max_wm_threads(uint32_t devid) in gen4_max_wm_threads() argument
120 return IS_GEN5(devid) ? 72 : IS_G4X(devid) ? 50 : 32; in gen4_max_wm_threads()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_chipset.h52 #define IS_945(devid) (devid == PCI_CHIP_I945_G || \ argument
53 devid == PCI_CHIP_I945_GM || \
54 devid == PCI_CHIP_I945_GME || \
55 devid == PCI_CHIP_G33_G || \
56 devid == PCI_CHIP_Q33_G || \
57 devid == PCI_CHIP_Q35_G || \
58 devid == PCI_CHIP_PNV_G || \
59 devid == PCI_CHIP_PNV_GM)
61 #define IS_GEN3(devid) (devid == PCI_CHIP_I915_G || \ argument
62 devid == PCI_CHIP_E7221_G || \
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/external/igt-gpu-tools/tools/
Dintel_error_decode.c95 print_instdone(uint32_t devid, unsigned int instdone, unsigned int instdone1) in print_instdone() argument
101 if (!init_instdone_definitions(devid)) in print_instdone()
238 print_pgtbl_err(unsigned int reg, unsigned int devid) in print_pgtbl_err() argument
240 if (IS_965(devid)) { in print_pgtbl_err()
242 } else if (IS_GEN3(devid)) { in print_pgtbl_err()
249 static void print_ivb_error(unsigned int reg, unsigned int devid) in print_ivb_error() argument
267 if (IS_HASWELL(devid) && (reg >> 10) & 0x1f) in print_ivb_error()
293 static void print_bdw_error(unsigned int reg, unsigned int devid) in print_bdw_error() argument
295 print_ivb_error(reg, devid); in print_bdw_error()
312 print_error(unsigned int reg, unsigned int devid) in print_error() argument
[all …]
Dintel_watermark.c37 static uint32_t devid; variable
242 int max_planes = skl_max_planes(devid); in skl_wm_dump()
255 int num_planes = skl_num_planes(devid, pipe); in skl_wm_dump()
265 if (plane != 0 && intel_gen(devid) < 11) in skl_wm_dump()
285 if (plane >= skl_num_planes(devid, pipe)) in skl_wm_dump()
299 if (plane >= skl_num_planes(devid, pipe)) in skl_wm_dump()
313 if (plane >= skl_num_planes(devid, pipe)) in skl_wm_dump()
326 if (plane >= skl_num_planes(devid, pipe)) in skl_wm_dump()
335 if (intel_gen(devid) >= 11) in skl_wm_dump()
342 if (plane >= skl_num_planes(devid, pipe)) in skl_wm_dump()
[all …]
Dintel_gtt.c43 uint32_t devid; variable
60 if (intel_gen(devid) < 8) in ingtt()
71 if (intel_gen(devid) < 4 && !IS_G33(devid)) in get_phys()
74 switch (intel_gen(devid)) { in get_phys()
82 if (IS_HASWELL(devid)) in get_phys()
108 if (intel_gen(devid) < 8) in pte_dump()
120 if (intel_gen(devid) < 8) { in pte_dump()
150 devid = pci_dev->device_id; in main()
152 if (IS_GEN2(devid)) { in main()
158 if (IS_GEN3(devid)) { in main()
[all …]
Dintel_display_poller.c97 static int pipe_to_plane(uint32_t devid, int pipe) in pipe_to_plane() argument
99 if (!IS_GEN2(devid) && !IS_GEN3(devid)) in pipe_to_plane()
126 static uint32_t dspoffset_reg(uint32_t devid, int pipe) in dspoffset_reg() argument
129 int plane = pipe_to_plane(devid, pipe); in dspoffset_reg()
131 if (IS_GEN2(devid) || IS_GEN3(devid)) in dspoffset_reg()
133 else if (IS_HASWELL(devid) || IS_BROADWELL(devid)) in dspoffset_reg()
144 static uint32_t dspsurf_reg(uint32_t devid, int pipe) in dspsurf_reg() argument
146 int plane = pipe_to_plane(devid, pipe); in dspsurf_reg()
148 if (IS_GEN2(devid) || IS_GEN3(devid)) in dspsurf_reg()
261 static void poll_pixel_pan(uint32_t devid, int pipe, int target_pixel, int target_fuzz, in poll_pixel_pan() argument
[all …]
Dintel_reg_decode.c55 int func(char *result, int len, int reg, uint32_t val, uint32_t devid)
87 if (!IS_MOBILE(devid)) in DEBUGSTRING()
90 if (IS_GEN4(devid)) { in DEBUGSTRING()
174 if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) in DEBUGSTRING()
187 if (IS_GEN2(devid) || IS_GEN3(devid)) in DEBUGSTRING()
195 if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) { in DEBUGSTRING()
199 if ((IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || in DEBUGSTRING()
200 IS_BROADWELL(devid) || IS_GEN9(devid))) in DEBUGSTRING()
228 } else if (IS_GEN4(devid) || IS_VALLEYVIEW(devid) || in DEBUGSTRING()
229 IS_CHERRYVIEW(devid)) { in DEBUGSTRING()
[all …]
Dintel_stepping.c49 uint32_t devid = pci_dev->device_id; in print_clock_info() local
52 if (IS_GM45(devid)) { in print_clock_info()
72 } else if (IS_965(devid) && IS_MOBILE(devid)) { in print_clock_info()
95 } else if (IS_945(devid) && IS_MOBILE(devid)) { in print_clock_info()
129 } else if (IS_915(devid) && IS_MOBILE(devid)) { in print_clock_info()
Dintel_l3_parity.c46 static unsigned int devid; variable
50 switch (intel_gt(devid)) { in num_banks()
64 #define MAX_SLICES (intel_gt(devid) > 1 ? 2 : 1)
86 if (IS_IVYBRIDGE(devid) || !(dft & 1)) { in decode_dft()
188 devid = intel_get_drm_devid(device); in main()
189 if (intel_gen(devid) < 7 || IS_VALLEYVIEW(devid)) in main()
260 printf("Has error injection: %s\n", IS_HASWELL(devid) ? "yes" : "no"); in main()
284 if (!IS_HASWELL(devid)) { in main()
Dintel_reg_checker.c32 static uint32_t devid; variable
169 if (intel_gt(devid) == 0) in check_gt_mode()
347 devid = dev->device_id; in main()
350 if (IS_GEN7(devid)) in main()
352 else if (IS_GEN6(devid)) in main()
354 else if (IS_GEN5(devid)) in main()
/external/u-boot/test/py/tests/
Dtest_mmc_rd.py108 def mmc_dev(u_boot_console, is_emmc, devid, partid): argument
122 cmd = 'mmc dev %d' % devid
131 good_response = 'mmc%d%s is current device' % (devid, partid_response)
149 devid = env__mmc_dev_config['devid']
153 mmc_dev(u_boot_console, is_emmc, devid, partid)
170 devid = env__mmc_dev_config['devid']
174 mmc_dev(u_boot_console, is_emmc, devid, partid)
196 devid = env__mmc_dev_config['devid']
204 mmc_dev(u_boot_console, is_emmc, devid, partid)
233 devid = env__mmc_rd_config['devid']
[all …]
Dtest_mmc_wr.py55 devid = env__mmc_wr_config['devid']
77 cmd = 'mmc dev %d' % devid
86 good_response = 'mmc%d%s is current device' % (devid, partid_response)
92 … 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % (devid, sector, count_sec…
98 …good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (devid, sector…
/external/igt-gpu-tools/tests/i915/
Di915_pm_rc6_residency.c106 static void read_residencies(int devid, unsigned int mask, in read_residencies() argument
115 (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))) in read_residencies()
127 static void measure_residencies(int devid, unsigned int mask, in measure_residencies() argument
139 read_residencies(devid, mask, &end); in measure_residencies()
145 read_residencies(devid, mask, &end); in measure_residencies()
201 unsigned int devid = 0; variable
210 devid = intel_get_drm_devid(fd);
228 measure_residencies(devid, rc6_enabled, &res);
235 igt_require(IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid));
237 measure_residencies(devid, rc6_enabled, &res);
Di915_getparams_basic.c38 int devid; variable
44 devid = intel_get_drm_devid(drm_fd); in init()
79 igt_skip_on_f(ret == -EINVAL && intel_gen(devid), "Interface not supported by kernel\n"); in subslice_total()
86 if ((intel_gen(devid) < 8) || in subslice_total()
87 IS_BROADWELL(devid) || in subslice_total()
123 if ((intel_gen(devid) < 8) || in eu_total()
124 IS_BROADWELL(devid) || in eu_total()
Dgem_exec_faulting_reloc.c58 uint32_t devid; variable
74 if (intel_gen(devid) >= 8) in gem_linear_blt()
90 if (intel_gen(devid) >= 8) in gem_linear_blt()
97 if (intel_gen(devid) >= 8) { in gem_linear_blt()
108 if (intel_gen(devid) >= 8) in gem_linear_blt()
118 if (intel_gen(devid) >= 8) in gem_linear_blt()
133 if (intel_gen(devid) >= 8) in gem_linear_blt()
140 if (intel_gen(devid) >= 8) { in gem_linear_blt()
151 if (intel_gen(devid) >= 8) in gem_linear_blt()
176 devid = intel_get_drm_devid(fd); in run()
[all …]
Di915_pm_lpsp.c34 static bool supports_lpsp(uint32_t devid) in supports_lpsp() argument
36 return IS_HASWELL(devid) || IS_BROADWELL(devid); in supports_lpsp()
64 drmModeConnectorPtr *drm_connectors, uint32_t devid, in edp_subtest() argument
135 if (IS_HASWELL(devid)) in edp_subtest()
187 uint32_t devid; variable
199 devid = intel_get_drm_devid(drm_fd);
211 igt_require(supports_lpsp(devid));
221 edp_subtest(drm_fd, drm_res, drm_connectors, devid, false);
223 edp_subtest(drm_fd, drm_res, drm_connectors, devid, true);
Dgem_tiling_max_stride.c66 uint32_t devid; variable
73 devid = intel_get_drm_devid(fd);
75 if (intel_gen(devid) >= 7) {
77 } else if (intel_gen(devid) >= 4) {
79 } else if (intel_gen(devid) >= 3) {
81 } else if (intel_gen(devid) >= 2) {
86 igt_skip("Unknown Intel chipset, devid=%04x\n", devid);
Dgem_non_secure_batch.c79 int devid; variable
82 devid = intel_get_drm_devid(fd);
84 if (HAS_BSD_RING(devid))
87 if (HAS_BLT_RING(devid))
97 batch = intel_batchbuffer_alloc(bufmgr, devid);
Dgem_pipe_control_store_loop.c50 uint32_t devid; variable
166 devid = intel_get_drm_devid(fd);
171 igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
172 igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
179 batch = intel_batchbuffer_alloc(bufmgr, devid);
Dgem_reloc_vs_gpu.c58 uint32_t devid; variable
72 if (intel_gen(devid) >= 8) { in create_special_bo()
86 if (intel_gen(devid) >= 8) in create_special_bo()
92 if (IS_GEN5(batch->devid)) { in create_special_bo()
109 if (IS_965(devid)) { in emit_dummy_load()
178 if (intel_gen(devid) >= 6) in reloc_and_emit()
279 batch = intel_batchbuffer_alloc(bufmgr, devid); in do_forked_test()
310 devid = intel_get_drm_devid(fd);
311 batch = intel_batchbuffer_alloc(bufmgr, devid);
/external/u-boot/drivers/pci/
Dpcie_layerscape_gen4_fixup.c52 u32 devid, u32 streamid) in ls_pcie_g4_lut_set_mapping() argument
55 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); in ls_pcie_g4_lut_set_mapping()
68 u32 devid, u32 streamid) in fdt_pcie_set_msi_map_entry() argument
95 fdt_appendprop_u32(blob, nodeoff, "msi-map", devid); in fdt_pcie_set_msi_map_entry()
110 u32 devid, u32 streamid) in fdt_pcie_set_iommu_map_entry() argument
137 iommu_map[0] = cpu_to_fdt32(devid); in fdt_pcie_set_iommu_map_entry()
142 if (devid == 0) in fdt_pcie_set_iommu_map_entry()

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