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Searched refs:dirty_level_mask (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Dr600_blit.c126 if (!staging && !texture->dirty_level_mask) in r600_blit_decompress_depth()
135 texture->dirty_level_mask = 0; in r600_blit_decompress_depth()
153 if (!staging && !(texture->dirty_level_mask & (1 << level))) in r600_blit_decompress_depth()
196 texture->dirty_level_mask &= ~(1 << level); in r600_blit_decompress_depth()
213 unsigned *dirty_level_mask; in r600_blit_decompress_depth_in_place() local
218 dirty_level_mask = &texture->stencil_dirty_level_mask; in r600_blit_decompress_depth_in_place()
221 dirty_level_mask = &texture->dirty_level_mask; in r600_blit_decompress_depth_in_place()
228 if (!(*dirty_level_mask & (1 << level))) in r600_blit_decompress_depth_in_place()
255 *dirty_level_mask &= ~(1 << level); in r600_blit_decompress_depth_in_place()
341 if (!rtex->dirty_level_mask) in r600_blit_decompress_color()
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Dr600_texture.c78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in r600_prepare_for_dma_blit()
90 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level)) in r600_prepare_for_dma_blit()
93 assert(!(rsrc->dirty_level_mask & (1 << src_level))); in r600_prepare_for_dma_blit()
94 assert(!(rdst->dirty_level_mask & (1 << dst_level))); in r600_prepare_for_dma_blit()
343 rtex->dirty_level_mask = 0; in r600_texture_discard_cmask()
1830 bool need_compressed_update = !tex->dirty_level_mask; in evergreen_do_fast_color_clear()
1832 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level; in evergreen_do_fast_color_clear()
Dr600_pipe_common.h211 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */ member
Dr600_state_common.c2427 rtex->dirty_level_mask |= 1 << surf->u.tex.level; in r600_draw_vbo()
2442 rtex->dirty_level_mask |= 1 << surf->u.tex.level; in r600_draw_vbo()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_blit.c233 texture->dirty_level_mask &= ~fully_decompressed_mask; in si_blit_decompress_zs_planes_in_place()
283 levels_z = level_mask & tex->dirty_level_mask; in si_decompress_depth()
336 tex->dirty_level_mask &= ~fully_copied_levels; in si_decompress_depth()
357 tex->dirty_level_mask &= ~levels_z; in si_decompress_depth()
423 level_mask &= tex->dirty_level_mask; in si_blit_decompress_color()
488 tex->dirty_level_mask &= ~(1 << level); in si_blit_decompress_color()
1058 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ in do_hardware_msaa_resolve()
1083 dst->dirty_level_mask &= ~(1 << info->dst.level); in do_hardware_msaa_resolve()
1194 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); in si_generate_mipmap()
Dsi_clear.c523 !(tex->dirty_level_mask & (1 << level))) { in si_do_fast_color_clear()
524 tex->dirty_level_mask |= 1 << level; in si_do_fast_color_clear()
571 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level); in si_clear()
Dsi_texture.c89 if (dst->cmask_buffer && dst->dirty_level_mask & (1 << dst_level)) { in si_prepare_for_dma_blit()
100 if (src->cmask_buffer && src->dirty_level_mask & (1 << src_level)) in si_prepare_for_dma_blit()
103 assert(!(src->dirty_level_mask & (1 << src_level))); in si_prepare_for_dma_blit()
104 assert(!(dst->dirty_level_mask & (1 << dst_level))); in si_prepare_for_dma_blit()
362 tex->dirty_level_mask = 0; in si_texture_discard_cmask()
521 tex->dirty_level_mask = new_tex->dirty_level_mask; in si_reallocate_texture_inplace()
Dsi_pipe.h339 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */ member
Dsi_state.c2533 tex->dirty_level_mask |= 1 << surf->u.tex.level; in si_update_fb_dirtiness_after_rendering()
2546 tex->dirty_level_mask |= 1 << surf->u.tex.level; in si_update_fb_dirtiness_after_rendering()
Dsi_descriptors.c488 (tex->dirty_level_mask && (tex->cmask_buffer || tex->surface.dcc_offset)); in color_needs_decompression()
/external/mesa3d/docs/relnotes/
D17.2.1.rst148 - radeonsi: update dirty_level_mask before dispatching