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/external/icu/android_icu4j/src/main/java/android/icu/impl/coll/
DBOCSU.java295 long division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff() local
296 int modulo = (int)division; in writeDiff()
298 diff = (int)(division >> 32); in writeDiff()
304 diff = (int)(division >> 32); in writeDiff()
305 division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff()
306 modulo = (int)division; in writeDiff()
307 diff = (int)(division >> 32); in writeDiff()
314 diff = (int)(division >> 32); in writeDiff()
315 division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff()
316 modulo = (int)division; in writeDiff()
[all …]
/external/icu/icu4j/main/classes/collate/src/com/ibm/icu/impl/coll/
DBOCSU.java294 long division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff() local
295 int modulo = (int)division; in writeDiff()
297 diff = (int)(division >> 32); in writeDiff()
303 diff = (int)(division >> 32); in writeDiff()
304 division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff()
305 modulo = (int)division; in writeDiff()
306 diff = (int)(division >> 32); in writeDiff()
313 diff = (int)(division >> 32); in writeDiff()
314 division = getNegDivMod(diff, SLOPE_TAIL_COUNT_); in writeDiff()
315 modulo = (int)division; in writeDiff()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Ddiv.ll3 ; Unsigned 8-bit division
13 ; Signed 8-bit division
23 ; Unsigned 16-bit division
33 ; Signed 16-bit division
43 ; Unsigned 32-bit division
54 ; Signed 32-bit division
65 ; Unsigned 64-bit division
82 ; Signed 64-bit division
99 ; Unsigned 128-bit division
108 ; Signed 128-bit division
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-div-01.ll1 ; Test vector division. There is no native integer support for this,
6 ; Test a v16i8 division.
29 ; Test a v8i16 division.
44 ; Test a v4i32 division.
55 ; Test a v2i64 division.
64 ; Test a v2f64 division.
74 ; Test an f64 division that uses vector registers.
Dint-div-06.ll5 ; Check signed 32-bit division.
18 ; Check unsigned 32-bit division.
29 ; Check signed 64-bit division.
46 ; Check unsigned 64-bit division.
Dvec-div-02.ll1 ; Test vector division on z14.
5 ; Test a v4f32 division.
15 ; Test an f32 division that uses vector registers.
Dint-div-03.ll1 ; Test 64-bit signed division and remainder when the divisor is
8 ; Test register division. The result is in the second of the two registers.
34 ; Test that division and remainder use a single instruction.
48 ; Test register division when the dividend is zero rather than sign extended.
71 ; Test memory division with no displacement.
99 ; Test both memory division and memory remainder.
194 ; a load and division cannot be combined.
Dfp-div-03.ll1 ; Test 128-bit floating-point division.
5 ; There is no memory form of 128-bit division.
/external/llvm/test/CodeGen/SystemZ/
Dvec-div-01.ll1 ; Test vector division. There is no native integer support for this,
6 ; Test a v16i8 division.
29 ; Test a v8i16 division.
44 ; Test a v4i32 division.
55 ; Test a v2i64 division.
64 ; Test a v2f64 division.
74 ; Test an f64 division that uses vector registers.
Dint-div-06.ll5 ; Check signed 32-bit division.
18 ; Check unsigned 32-bit division.
29 ; Check signed 64-bit division.
46 ; Check unsigned 64-bit division.
Dint-div-03.ll1 ; Test 64-bit signed division and remainder when the divisor is
8 ; Test register division. The result is in the second of the two registers.
34 ; Test that division and remainder use a single instruction.
48 ; Test register division when the dividend is zero rather than sign extended.
71 ; Test memory division with no displacement.
99 ; Test both memory division and memory remainder.
194 ; a load and division cannot be combined.
Dfp-div-03.ll1 ; Test 128-bit floating-point division.
5 ; There is no memory form of 128-bit division.
/external/FXdiv/
DMETADATA3 "Header-only library for division via fixed-point multiplication by inverse "
5 "On modern CPUs and GPUs integer division is several times slower than "
7 "division with a multiplication and two shifts. This algorithm improves "
DREADME.md7 Header-only library for division via fixed-point multiplication by inverse
9 …s and GPUs integer division is several times slower than multiplication. FXdiv implements an algor…
13 - Integer division for `uint32_t`, `uint64_t`, and `size_t`
/external/u-boot/doc/device-tree-bindings/clock/
Dst,stm32mp1.txt53 0x1: division by 2
54 0x2: division by 4
55 0x3: division by 8
60 0x1: division by 2
61 0x2: division by 3
62 0x3: division by 4
93 0x0: bypass (division by 1)
94 0x1: division by 2
95 0x2: division by 3
96 0x3: division by 4
/external/tensorflow/tensorflow/
D__init__.py20 from __future__ import division
31 del division
/external/tensorflow/tensorflow/python/keras/preprocessing/
D__init__.py18 from __future__ import division
33 del division
/external/tensorflow/tensorflow/python/keras/
D__init__.py21 from __future__ import division
43 del division
/external/tensorflow/tensorflow/python/saved_model/
Dsignature_def_utils.py20 from __future__ import division
36 del division
/external/tensorflow/tensorflow/python/ops/
Dinitializers_ns.py18 from __future__ import division
43 del division
/external/bc/manuals/
Dalgorithms.md35 This `bc` uses Algorithm D ([long division][2]). Long division is polynomial
36 (`O(n^2)`), but unlike Karatsuba, any division "divide and conquer" algorithm
38 algorithms become less attractive with division as this operation typically
41 While the implementation of long division may appear to use the subtractive
52 Using multiplication would make division have the even worse algorithmic
65 operation. Its complexity is `O(log(n)*n^2)` as it requires one division per
/external/llvm/test/CodeGen/X86/
Dfdiv-combine.ll3 ; More than one 'arcp' division using a single divisor operand
6 ; Don't do anything for just one division.
34 ; The first division is not 'arcp', so do not optimize.
49 ; The second division is not 'arcp', so do not optimize.
/external/tensorflow/tensorflow/python/keras/utils/
Dall_utils.py22 from __future__ import division
47 del division
/external/tensorflow/tensorflow/python/ops/linalg/
Dlinalg.py18 from __future__ import division
50 del division
/external/u-boot/arch/arm/lib/
Ddiv64.S87 @ The division loop for needed upper bit positions.
103 @ The division loop for lower bit positions.
143 @ If possible, branch for another shift in the division loop.
190 @ eq -> division by 1: obvious enough...

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