1STMicroelectronics STM32MP1 clock tree initialization 2===================================================== 3 4The STM32MP1 clock tree initialization is based on device tree information 5for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes. 6 7RCC IP = st,stm32mp1-rcc 8======================== 9 10The RCC IP is both a reset and a clock controller but this documentation only 11describes the fields added for clock tree initialization which are not present 12in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt 13file. 14 15The added properties for clock tree initialization are: 16 17Required properties: 18- st,clksrc : The clock sources configuration array in a platform specific 19 order. 20 21 For the STM32MP15x family there are 9 clock sources selector which are 22 configured in the following order: 23 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2 24 25 Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE> 26 from dt-bindings/clock/stm32mp1-clksrc.h. 27 28 Example: 29 st,clksrc = < 30 CLK_MPU_PLL1P 31 CLK_AXI_PLL2P 32 CLK_MCU_PLL3P 33 CLK_PLL12_HSE 34 CLK_PLL3_HSE 35 CLK_PLL4_HSE 36 CLK_RTC_LSE 37 CLK_MCO1_DISABLED 38 CLK_MCO2_DISABLED 39 >; 40 41- st,clkdiv : The clock main dividers value specified in an array 42 in a platform specific order. 43 44 When used, it shall describe the whole clock dividers tree. 45 46 For the STM32MP15x family there are 11 dividers values expected. 47 They shall be configured in the following order: 48 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2 49 50 The each divider value uses the DIV coding defined in RCC associated 51 register RCC_xxxDIVR. In most the case, it is: 52 0x0: not divided 53 0x1: division by 2 54 0x2: division by 4 55 0x3: division by 8 56 ... 57 58 Note that for RTC MCO1 MCO2, the coding is different: 59 0x0: not divided 60 0x1: division by 2 61 0x2: division by 3 62 0x3: division by 4 63 ... 64 65 Example: 66 st,clkdiv = < 67 1 /*MPU*/ 68 0 /*AXI*/ 69 0 /*MCU*/ 70 1 /*APB1*/ 71 1 /*APB2*/ 72 1 /*APB3*/ 73 1 /*APB4*/ 74 2 /*APB5*/ 75 23 /*RTC*/ 76 0 /*MCO1*/ 77 0 /*MCO2*/ 78 >; 79 80Optional Properties: 81- st,pll : A specific PLL configuration, including frequency. 82 83 PLL children nodes for PLL1 to PLL4 (see ref manual for details) 84 are listed with associated index 0 to 3 (st,pll@0 to st,pll@3). 85 PLLx is off when the associated node is absent. 86 87 Here are the available properties for each PLL node: 88 89 - cfg: The parameters for PLL configuration in the following order: 90 DIVM DIVN DIVP DIVQ DIVR Output. 91 92 DIVx values are defined as in RCC spec: 93 0x0: bypass (division by 1) 94 0x1: division by 2 95 0x2: division by 3 96 0x3: division by 4 97 ... 98 99 Output contains a bitfield for each output value (1:ON/0:OFF) 100 BIT(0) => output P : DIVPEN 101 BIT(1) => output Q : DIVQEN 102 BIT(2) => output R : DIVREN 103 NB: macro PQR(p,q,r) can be used to build this value 104 with p,q,r = 0 or 1. 105 106 - frac : Fractional part of the multiplication factor 107 (optional, PLL is in integer mode when absent). 108 109 - csg : Clock Spreading Generator (optional) with parameters in the 110 following order: MOD_PER INC_STEP SSCG_MODE. 111 112 MOD_PER: Modulation Period Adjustment 113 INC_STEP: Modulation Depth Adjustment 114 SSCG_MODE: Spread spectrum clock generator mode, with associated 115 defined from stm32mp1-clksrc.h: 116 - SSCG_MODE_CENTER_SPREAD = 0 117 - SSCG_MODE_DOWN_SPREAD = 1 118 119 Example: 120 st,pll@0 { 121 cfg = < 1 53 0 0 0 1 >; 122 frac = < 0x810 >; 123 }; 124 st,pll@1 { 125 cfg = < 1 43 1 0 0 PQR(0,1,1) >; 126 csg = < 10 20 1 >; 127 }; 128 st,pll@2 { 129 cfg = < 2 85 3 13 3 0 >; 130 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; 131 }; 132 st,pll@3 { 133 cfg = < 2 78 4 7 9 3 >; 134 }; 135 136- st,pkcs : used to configure the peripherals kernel clock selection. 137 138 The property is a list of peripheral kernel clock source identifiers defined 139 by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file 140 dt-bindings/clock/stm32mp1-clksrc.h. 141 142 st,pkcs may not list all the kernel clocks and has no ordering requirements. 143 144 Example: 145 st,pkcs = < 146 CLK_STGEN_HSE 147 CLK_CKPER_HSI 148 CLK_USBPHY_PLL2P 149 CLK_DSI_PLL2Q 150 CLK_I2C46_HSI 151 CLK_UART1_HSI 152 CLK_UART24_HSI 153 >; 154 155other clocks = fixed-clock 156========================== 157 158The clock tree is also based on 5 fixed-clock in clocks node 159used to define the state of associated ST32MP1 oscillators: 160 - clk-lsi 161 - clk-lse 162 - clk-hsi 163 - clk-hse 164 - clk-csi 165 166At boot the clock tree initialization will 167 - enable oscillators present in device tree and not disabled 168 (node with status="disabled"), 169 - disable HSI oscillator if the node is absent (always activated by bootrom) 170 and not disabled (node with status="disabled"). 171 172Optional properties : 173 174a) for external oscillator: "clk-lse", "clk-hse" 175 176 4 optional fields are managed 177 - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP) 178 - "st,digbypass" configures the bypass mode as full-swing digital 179 signal (DIGBYP) 180 - "st,css" activates the clock security system (HSECSSON, LSECSSON) 181 - "st,drive" (only for LSE) contains the value of the drive for the 182 oscillator (see LSEDRV_ defined in the file 183 dt-bindings/clock/stm32mp1-clksrc.h) 184 185 Example board file: 186 / { 187 clocks { 188 clk_hse: clk-hse { 189 #clock-cells = <0>; 190 compatible = "fixed-clock"; 191 clock-frequency = <64000000>; 192 st,bypass; 193 }; 194 195 clk_lse: clk-lse { 196 #clock-cells = <0>; 197 compatible = "fixed-clock"; 198 clock-frequency = <32768>; 199 st,css; 200 st,drive = <LSEDRV_LOWEST>; 201 }; 202 }; 203 204b) for internal oscillator: "clk-hsi" 205 206 Internally HSI clock is fixed to 64MHz for STM32MP157 SoC. 207 In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC 208 doc). So this clock frequency is used to compute the expected HSI_DIV 209 for the clock tree initialization. 210 211 Example with HSIDIV = /1: 212 / { 213 clocks { 214 clk_hsi: clk-hsi { 215 #clock-cells = <0>; 216 compatible = "fixed-clock"; 217 clock-frequency = <64000000>; 218 }; 219 }; 220 221 Example with HSIDIV = /2 222 / { 223 clocks { 224 clk_hsi: clk-hsi { 225 #clock-cells = <0>; 226 compatible = "fixed-clock"; 227 clock-frequency = <32000000>; 228 }; 229 }; 230 231Example of clock tree initialization 232==================================== 233 234/ { 235 clocks { 236 u-boot,dm-pre-reloc; 237 clk_hse: clk-hse { 238 u-boot,dm-pre-reloc; 239 #clock-cells = <0>; 240 compatible = "fixed-clock"; 241 clock-frequency = <24000000>; 242 st,digbypass; 243 }; 244 245 clk_hsi: clk-hsi { 246 u-boot,dm-pre-reloc; 247 #clock-cells = <0>; 248 compatible = "fixed-clock"; 249 clock-frequency = <64000000>; 250 }; 251 252 clk_lse: clk-lse { 253 u-boot,dm-pre-reloc; 254 #clock-cells = <0>; 255 compatible = "fixed-clock"; 256 clock-frequency = <32768>; 257 }; 258 259 clk_lsi: clk-lsi { 260 u-boot,dm-pre-reloc; 261 #clock-cells = <0>; 262 compatible = "fixed-clock"; 263 clock-frequency = <32000>; 264 }; 265 266 clk_csi: clk-csi { 267 u-boot,dm-pre-reloc; 268 #clock-cells = <0>; 269 compatible = "fixed-clock"; 270 clock-frequency = <4000000>; 271 }; 272 }; 273 274 soc { 275 276 rcc: rcc@50000000 { 277 u-boot,dm-pre-reloc; 278 compatible = "st,stm32mp1-rcc", "syscon"; 279 reg = <0x50000000 0x1000>; 280 #clock-cells = <1>; 281 #reset-cells = <1>; 282 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 283 284 st,clksrc = < 285 CLK_MPU_PLL1P 286 CLK_AXI_PLL2P 287 CLK_MCU_PLL3P 288 CLK_PLL12_HSE 289 CLK_PLL3_HSE 290 CLK_PLL4_HSE 291 CLK_RTC_LSE 292 CLK_MCO1_DISABLED 293 CLK_MCO2_DISABLED 294 >; 295 296 st,clkdiv = < 297 1 /*MPU*/ 298 0 /*AXI*/ 299 0 /*MCU*/ 300 1 /*APB1*/ 301 1 /*APB2*/ 302 1 /*APB3*/ 303 1 /*APB4*/ 304 2 /*APB5*/ 305 23 /*RTC*/ 306 0 /*MCO1*/ 307 0 /*MCO2*/ 308 >; 309 310 st,pkcs = < 311 CLK_CKPER_HSE 312 CLK_FMC_ACLK 313 CLK_QSPI_ACLK 314 CLK_ETH_DISABLED 315 CLK_SDMMC12_PLL4P 316 CLK_DSI_DSIPLL 317 CLK_STGEN_HSE 318 CLK_USBPHY_HSE 319 CLK_SPI2S1_PLL3Q 320 CLK_SPI2S23_PLL3Q 321 CLK_SPI45_HSI 322 CLK_SPI6_HSI 323 CLK_I2C46_HSI 324 CLK_SDMMC3_PLL4P 325 CLK_USBO_USBPHY 326 CLK_ADC_CKPER 327 CLK_CEC_LSE 328 CLK_I2C12_HSI 329 CLK_I2C35_HSI 330 CLK_UART1_HSI 331 CLK_UART24_HSI 332 CLK_UART35_HSI 333 CLK_UART6_HSI 334 CLK_UART78_HSI 335 CLK_SPDIF_PLL4P 336 CLK_FDCAN_PLL4Q 337 CLK_SAI1_PLL3Q 338 CLK_SAI2_PLL3Q 339 CLK_SAI3_PLL3Q 340 CLK_SAI4_PLL3Q 341 CLK_RNG1_LSI 342 CLK_RNG2_LSI 343 CLK_LPTIM1_PCLK1 344 CLK_LPTIM23_PCLK3 345 CLK_LPTIM45_LSE 346 >; 347 348 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 349 pll1: st,pll@0 { 350 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 351 frac = < 0x800 >; 352 u-boot,dm-pre-reloc; 353 }; 354 355 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), 356 R = 533 (DDR) */ 357 pll2: st,pll@1 { 358 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 359 frac = < 0x1400 >; 360 u-boot,dm-pre-reloc; 361 }; 362 363 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 364 pll3: st,pll@2 { 365 cfg = < 1 33 1 16 36 PQR(1,1,1) >; 366 frac = < 0x1a04 >; 367 u-boot,dm-pre-reloc; 368 }; 369 370 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 371 pll4: st,pll@3 { 372 cfg = < 3 98 5 7 7 PQR(1,1,1) >; 373 u-boot,dm-pre-reloc; 374 }; 375 }; 376 }; 377}; 378